ST Nucleo + SEGGER Jlink adapter

[dadler]

I wanted to use my SEGGER Jlink with my ST Nucleo dev boards, so I made an adapter:



There are a bunch of different ways this could have been done, but I wanted a single adapter board and way of tapping into the target Vref without additional flying leads.

For some reason, ST populated D1 (BAT60JFILM) and R1 (10k pulldown), but left R9 unpopulated. Even if you populate R9, the other side is connected to AIN_1, which is a 4k7/4k7 potential divider from 3.3V and hence sits at ~1.65V. I'm not sure what the plan was here, but I decided to tap into 3.3V without modifying the board.

On the adapter, target Vref is tapped into JP1 (3.3V) on the Nucleo PCB, which is left open from the factory. JP1 controls the max current requested during USB enumeration. You may need to short it if you are powering the board via USB without enumeration. If you wish to short this jumper, use extended-length header pins or simply bridge the pins on the adapter PCB.

On the adapter, I connected pin 1 of the SWD connector (CN4) to target Vref, but this was unnecessary. It just felt like the right thing to do. Hehe.

Anyways, if you are interested in the layout files they are here:

https://github.com/dustinadler/nucleo-jlink

The board is available on OSH Park:

https://oshpark.com/shared_projects/m3tkYXXR

More pictures:

[nano]

Simple and nice! I like it.

[charlespax]

OMG that's awesome! I need to make some 

[jnz]

Very nicely done!

[dadler]

Thanks everyone!

Personally, I find st-link to be extremely flakey (I primarily use Unix/Mac development machines+Eclipse). Lots of USB issues, required power cycling, etc.

On the other hand, the SEGGER hardware/tools are polished and "just work". I also find the debugging experience via the SEGGER tools to be much improved over OpenOCD.

I found the process of manually connecting the Jlink with jumper leads to be tedious and error prone, and hence I made this extremely simple adapter.

The layout/configuration is a result of my desire to have the 20 pin IDC cable/terminations in an orientation that seems natural when positioning the Jlink vs Nucleo board on your workbench.

One other note: Due to the positioning of the IDC socket on the adapter, the UART tx/rx pins are somewhat occluded. This is easily worked around if you need those pins, though.

[richardman]

FWIW, it looks like ST and Segger have an agreement to turn your ST-LINK into a Segger JLINK:
http://www2.st.com/content/st_com/en/products/development-tools/hardware-development-tools/development-tool-hardware-for-mcus/debug-hardware-for-mcus/debug-hardware-for-stm32-mcus/seg-jlink.html

Have not tried it yet, but as I have a half dozen+ ST-Nucleo lying around, I will no doubt try it out soon.

[charlespax]

FWIW, it looks like ST and Segger have an agreement to turn your ST-LINK into a Segger JLINK:
http://www2.st.com/content/st_com/en/products/development-tools/hardware-development-tools/development-tool-hardware-for-mcus/debug-hardware-for-mcus/debug-hardware-for-stm32-mcus/seg-jlink.html

Have not tried it yet, but as I have a half dozen+ ST-Nucleo lying around, I will no doubt try it out soon.

That's amazing! I'm shocked this is the first time I've heard to this. Here is the corresponding Segger link https://www.segger.com/jlink-st-link.html

The limitations are:

• May be used with ARM based ST devices only
• Only debugging on evaluation boards is allowed. Debugging on custom hardware is not supported and not allowed
• No production flash programming support
• Unlimited breakpoints in flash available for evaluation only
• No support is given

[Kjelt]

It was only recently released 

•Only debugging on evaluation boards is allowed. Debugging on custom hardware is not supported and not allowed

How will/can they enforce that ?

[richardman]

It was only recently released 

•Only debugging on evaluation boards is allowed. Debugging on custom hardware is not supported and not allowed

How will/can they enforce that ?

Segger has a habit of "enforcement by not giving you the time of day". I suspect that it really is as simple as: if you are a commercial developer, and not in a country like China or India, and if we find out you violate our terms and conditions, you are sh*te to us.

[dannyf]

It was only recently released 

only outside of China,

it has been looooong suspected that those ST-Links are nothing but J-Links with specialized firmware. The V9 hardware is based on a STM32 chip. And there is a j-link OB firmware piece floating around based on F072 -> if you flash a 072 discovery board or a nucleo board with that thing, it becomes a full-blown j-link (OB albeit). The simplest implementation of it contains just the chip + firmware.

So time to rush out and get a few of those 072 boards now,

[richardman]

That will certainly violate their terms and conditions, and as a commercial vendor, I request that this forum not be a place to discuss such matters.

[dannyf]

the st-link on those boards are v2-1, so they are perfect candidate to use the utilities mentioned earlier to be flashed to a jlink (with some limitations). It does provide you an opportunity to try out interesting features not otherwise available on the st-link.

If you don't like it, you can always flash it back, using the same utilities.