synthesize basics

[mn]

I have synthesized a simple 1 bit full adder with ISE which consists of 2 half adders and an OR gate. The Half adder entity also consists of an XOR and an AND gates. What I get as results are:

1- The output shows that only 2 XOR gates were used!

Code: [Select]

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# Xors                                                 : 2
1-bit xor2                                            : 2

=========================================================================
2- The RTL schematic of the FA correctly shows two half adders and an OR gate. However, the RTL schematic of half adders only shows one input port (!) and it considers a bus (!) names data[1:0] instead of x and y as inputs. Please see the attachments (1.jpg and 2.jpg).


3- The Planahead correctly maps the design to two 3-LUTs as the attachment (3.jpg).

4- Observing the device, I see that two LUTs are merged in one LUT which I don't understand that! (4.jpg)

Any comment for the mentioned items?

[radar_macgyver]

1- The output shows that only 2 XOR gates were used!

The report only shows any macros that were found, it doesn't include every LUT.

2- The RTL schematic of the FA correctly shows two half adders and an OR gate. However, the RTL schematic of half adders only shows one input port (!) and it considers a bus (!) names data[1:0] instead of x and y as inputs. Please see the attachments (1.jpg and 2.jpg).

Nothing wrong with the results, but yes the naming is not consistent. The 'x' bus at the input of the HA is split up before going to the carry AND, and the XOR is shown as a macro.

4- Observing the device, I see that two LUTs are merged in one LUT which I don't understand that! (4.jpg)

Nothing wrong with the merge either, the 6-LUTs in your device can implement the entire full adder in one LUT since they have two outputs. This minimizes routing between LUTs. on a 4-LUT device (Virtex-5 and below, or Spartan-3 and below) this would always need two LUTs. Map has a LUT packing option, but that's for unrelated logic, and relates to packing unrelated LUTs into CLBs (if I recall correctly).

[mn]

Thank you very much

[mrflibble]

Internally a LUT6 is built out of two LUT5s and a MUX. From UG384:

The function generators in Spartan-6 FPGAs are implemented as six-input look-up tables
(LUTs). There are six independent inputs (A inputs - A1 to A6) and two independent
outputs (O5 and O6) for each of the four function generators in a slice (A, B, C, and D). The
function generators can implement any arbitrarily defined six-input Boolean function.
Each function generator can also implement two arbitrarily defined five-input Boolean   
functions, as long as these two functions share common inputs. Only the O6 output of the
function generator is used when a six-input function is implemented. Both O5 and O6 are
used for each of the five-input function generators implemented.




See https://www.xilinx.com/support/documentation/user_guides/ug384.pdf for more info.