SystemVerilog - handling multiple interfaces as an array - how to write

[daqq]

Hi guys,

Is there any way to write this:

Code: [Select]

module SimpleBusExpander(
input Clock,
input ResetN,
Interface_SimpleBus.Slave BusIn,

Interface_SimpleBus.Master BusOut0,
Interface_SimpleBus.Master BusOut1,
Interface_SimpleBus.Master BusOut2,
...
Interface_SimpleBus.Master BusOut15
    );
into something like

Code: [Select]

module SimpleBusExpander(
input Clock,
input ResetN,
Interface_SimpleBus.Slave BusIn,

Interface_SimpleBus.Master BusOutArray[15:0]
    );
?
I've tried some variations, but they all end up with all sorts of compilation errors. My goal is to be able to do something like this:

Code: [Select]

    assign BusIn.ReadData = BusOut[BusIn.Address[19:16]].ReadData;
    assign BusIn.Acknowledge = BusOut[BusIn.Address[19:16]].Acknowledge;
    assign BusIn.Error = BusOut[BusIn.Address[19:16]].Error;without a million repeating lines of code.

Thanks,

David

[mrflibble]

Is this for verification only, or also for synthesis? If synthesis, what tool are you using?

If this was for Xilinx I know I would be explicitely checking if this is supported. Because yes Xilinx tools support interfaces for synthesis (and Altera as well AFAIK), but I would not count on them implementing the full spec without double checking things. The best sanity check for "Is this valid SystemVerilog?" is usually to read the LRM or to run it through Modelsim. Modelsim adheres pretty closely to the standard in my (admittedly limited) experience. With Xilinx it's a crapshoot, and for Altera I hear it's a little better but not by much.

You could make Interface_SimpleBus a parameterized interface, complete with the modport you already have. The parameter would be the array size. Another option would be to try a non-ansi port declaration, and see if the synthesis vendor du jour did implement interface arrays for that.

Worst case you could use a generate block to do something similar to those assign statements, but that is just stupid. If that is the only thing that works it is still better than 256 assign statements, but there really should be something better that is supported by synthesis tools.

Based on other implemented featured (for Xilinx) I'd give the parameterized interface a reasonable chance of success, but only one way to find out.

[daqq]

Thanks for the suggestions. The generate command seems workable, I'll try fiddling with that - based on your description, seems safer  .

Yes, this is for synthesis as well and I'm using Xilinx Vivado tools, for the Zynq 7000 device.

Thanks,

David

[mrflibble]

I just checked the LRM and I think that the port syntax you tried to use is illegal. But the non-ansi syntax as suggested earlier is legal. Anyways, generate is bound to work. A bit of a blunt instrument, but if it works for you who cares.