Let's make it clear. The 100 conversions should start on the last falling edge of a PWM burst. With minimum jitter.
The minimum jitter means the sequence of 100 conversions must be started by hardware.
To do this several approaches have been described here.
One of which is using the DMA to stop
storing the samples.
Meaning the ADC could be in continuous mode, and some other hardware triggered the DMA Channel Enable bit.
The ADC has few operational modes.
- One sequence.
- Continuous.
Let's forget injected for a moment here.
The DMA is triggered
by the ADC for each End-Of-Conversion, any conversion, including those within a sequence.
Performing sequence conversion on the ADC, performs the amount of DMA operations as channels in the sequence.
Performing continuous conversions on the ADC,
stores DMA CNDTR conversions. Or infinite when circular is enabled.
Using CNDTR as the counter to 100 is possible, low jitter was requested something still has to do either of these:
- Enable the DMA channel by hardware while the ADC is in continous. Maximum latency is the sequence time.
- Enable the ADC continuous mode by hardware. Maximum latency is ADC start delay.
Recommended reading:
AN3116 Application STM32™’s ADC modes and their applicationsNow, I think it is possible to perform this completely in hardware, except resetting the hardware.
- Use a timer X to detect the PWM burst, and enable a timer Y after n edges. (assuming fixed edge count*)
- This timer Y triggers the ADC sequence conversions, not once but infinitely.
- DMA counts to 100, the DMA Complete IRQ is set.
- In the ISR, reset timer X, stop and reset timer Y and reset the DMA. And do something with your data, obviously.
*now, timeout triggering can probably also be done. By connecting timer X external trigger to reset mode, with countdown mode. The update event should TRGO to timer Y to enable it. I have never tried this.