Typical speed of FPGAs

[gaffer]

I'm about to but a development kit but not sure which one but I'm looking at the MachXO 2280 Breakout Board http://uk.rs-online.com/web/p/programmable-logic-development-kits/7434788/

Can anyone tell me the speed of just 1 logic gate and the speed of 100 in series?
I have a great project in mind and any advice appreciated, I want the fastest.
Thanks

Paul.

[funkathustra]

Can anyone tell me the speed of just 1 logic gate and the speed of 100 in series?

FPGAs don't have logic gates, so I'm not sure what you're asking. Are you talking about input and output buffers on pads?

I have a great project in mind and any advice appreciated, I want the fastest.

You want the fastest FPGA? I think the 16 nm Virtex 7 is probably going to be the fastest (or at least one of the fastest). It has a minimum pad-to-pad delay of 0.288 nanoseconds in the -3 speed grade (obviously from a high-speed LV diff pair — not sure about standard single-ended pads). Most of these have a GCLK that tops out at about 1 GHz, so that should give you an idea of how "fast" they'll be, given you LUT usage, etc.

When you synthesize and fit your VHDL/Verilog design, you'll be able to get timing reports from your FPGA development software. I'm not smart enough to figure that stuff out on my own, so I just let the tools do the thinking for me.

Maybe you should tell us more about your project?

[tggzzz]

Often the gate delay is dwarfed by the interconnection (wire) delay. The latter is highly dependent on where the gates are placed.

So there's no useful answer to your question.

[gaffer]

Can anyone tell me the speed of just 1 logic gate and the speed of 100 in series?

FPGAs don't have logic gates, so I'm not sure what you're asking. Are you talking about input and output buffers on pads?

I have a great project in mind and any advice appreciated, I want the fastest.

You want the fastest FPGA? I think the 16 nm Virtex 7 is probably going to be the fastest (or at least one of the fastest). It has a minimum pad-to-pad delay of 0.288 nanoseconds in the -3 speed grade (obviously from a high-speed LV diff pair — not sure about standard single-ended pads). Most of these have a GCLK that tops out at about 1 GHz, so that should give you an idea of how "fast" they'll be, given you LUT usage, etc.

When you synthesize and fit your VHDL/Verilog design, you'll be able to get timing reports from your FPGA development software. I'm not smart enough to figure that stuff out on my own, so I just let the tools do the thinking for me.

Maybe you should tell us more about your project?

http://uk.rs-online.com/web/c/semiconductors/programmable-logic-circuits/fpgas/

FPGA's  are  programmable logic circuits for And, xor ,nand etc.
I wish to develop my own processor using logic gates but as will require 1000+ gates I looked in to chips that contain many, and came across fpga's.
I really need it as fast as possible, you quoted 0.288 ns. Is this typical? Can I use 100's in series per clock cycle or is it 1 logic per cycle?

http://uk.rs-online.com/web/p/standard-logic-gates/8168797/  for example is a single logic gate chip with a Maximum Propagation Delay Time of 7.5 ns. I would use something like these but soldering 1000+ would take a long time.
I would like faster, if anyone has any advice.
May not be an fpga but intel Pentium processors are like 3.8G a second though not sure if that speed is per thread or total threads?
Thanks.

Just checked out  http://www.analog.com/en/products/high-speed-logic/logic-devices/logic-gates.html
That have a range at 45 Gbps. This is good though I don't want to solder 1000's.
Any advice?
Thanks.

[DaJMasta]

It's really difficult to give you a figure like that, because individual logic gates are not accessible in an FPGA (or if they are, a large chunk of stuff associated with them is disabled and they don't necessarily equate to a normal discrete gate).  It's also a great point that the propagation delay of the individual elements can be a huge hard limit on how fast a complete system can operate - and this applies doubly to trying to build something so complex out of discrete logic.  FPGAs are all about parallelism and building in the elements you need in the quantities you need, and that's where the performance comes from - not just raw clockspeed.

FPGAs are fast enough compared to discrete logic just because of the advantages that a small die and physically close elements can get you that a soft core in an FPGA running at maybe 50MHz or better will outperform identical configuration discrete gates even with optimal layout and high speed gates (and I think that's being pretty generous).  Your pipeline gets long enough that the additional propagation delay through the length of the wires on the board (even if signal integrity and power distribution is fine) is a significant top speed limiter.  Of course, architecture will make a huge speed difference too, and one advantage with an FPGA is that you can reconfigure your architecture to try and optimize performance with just some recompiled software.

You can use 100 gates in series in a single clock cycle in the same way as discrete logic - have a 100 stage pipeline and data processing at every element.  The time it takes for a given piece to get through is still going to be 100 cycles, but you can have 100 pieces of data in there at once.  If you're really that concerned with speed, though, why are you even considering a discrete logic processor?  You're going to be able to hit a few MHz , tops, with discrete parts, so almost any FPGA will likely outperform it.

[MK14]

[chris_leyson]

Until recently I was writing some VHDL for very fast pipelined FFTs which would have gone onto a Zynq7010 or 7020, never got around to finishing the project, company is about to go into administration, but ball park estimate for the high speed parts was 250MHz maybe even 300MHz. Will have to put that project on the back burner for now.

[gaffer]

Just checked out  http://www.analog.com/en/products/high-speed-logic/logic-devices/logic-gates.html
That have a range at 45 Gbps. This is good though I don't want to solder 1000's.
Any advice?
Thanks.

[MK14]

Just checked out  http://www.analog.com/en/products/high-speed-logic/logic-devices/logic-gates.html
That have a range at 45 Gbps. This is good though I don't want to solder 1000's.
Any advice?
Thanks.

EDIT: Cancelled. Please ignore.
At this point, it would seem you are trolling.
If I am wrong, sorry.
If I am right, you have probably been here before ...

[legacy]

the high speed parts was 250MHz maybe even 300MHz

Yup. And we can scale down to 50-100Mhz for hobby.

[legacy]

intel Pentium processors are like 3.8G

CPUs are ASIC design. Completely different in every aspect.
btw, which kind of softcore are you willing to do?

[chris_leyson]

  :-BROKEThanks legacy, I had forgotten about the hobby aspect, but 50MHz to 100MHz is probably about ball park for the lower speed and lower cost FPGAs. I hadn't even checked the prices for the high end Zynq parts let alone the cost of a 500fps camera. Got a few Spartan3 dev boards knocking around and they manage 50MHz with no problems and even 100MHz if you are careful. EDIT: Just read the lattice data sheet, you can STILL do some cool stuff with 2280 LUTs.

[tggzzz]

I wish to develop my own processor using logic gates but as will require 1000+ gates I looked in to chips that contain many, and came across fpga's.
I really need it as fast as possible, you quoted 0.288 ns. Is this typical? Can I use 100's in series per clock cycle or is it 1 logic per cycle?

And when you have developed your own processor, then what? How are you going to program it?

When you say "as fast as possible" do you mean lowest latency or highest throughput or shortest clock cycle?

A CLB delay of 288ps is probably reasonable - and completely irrelevant since the interconnection delays will dominate. It is quite possible that it would take an extra 1000ps for the signal to reach the destination.

I suggest you buy the cheapest FPGA board available, and create some "hello world" applications from beginning to end. That will allow you to explore possibilities and understand constraints. And at that point you will be in a better position to ask questions that can be answered.

[funkathustra]

FPGA's [sic]  are  programmable logic circuits for And, xor ,nand etc.

No, you're mistaken. Yes, they are programmable logic; but they are not "programmable logic gates" — internally, they use look-up tables (LUTs) and digital muxes. This is an extremely basic concept that a sophomore student would learn in the first lecture in their FPGA class. You don't even begin to possess the concepts you'd need to do what you're talking about.

May not be an fpga but intel Pentium processors are like 3.8G a second though not sure if that speed is per thread or total threads?

Completely irrelevant to FPGAs.

Just checked out  http://www.analog.com/en/products/high-speed-logic/logic-devices/logic-gates.html
That have a range at 45 Gbps. This is good though I don't want to solder 1000's. Any advice?

Given the lack of quality in the questions you're asking, I really don't think you have the skill set or experience to work on a project in the manner that you are talking about.

Processors constructed on FPGAs are always going to be much slower and use much more power than an ASIC version of the processor constructed on the same process. Soft-core processors are used in very specific instances when a processor needs to be extended with custom peripherals on the bus, or in research/academic situations. Most modern high-end FPGA-based designs that have processor requirements use a hybrid chip that has both FPGA fabric and a hardware IP processor built-in (usually an ARM processor these days).

If you are interested in learning about implementing processor cores on an FPGA to learn about how they work, there are much better questions to ask. But obviously that's done as a learning exercise; not as a means to actually obtain a fast processor.

Go buy a basic CPLD or FPGA dev board, start working through some basic projects on it, and you'll quickly learn how they work.

[sporadic]

I was really looking forward to some discrete logic 45gbps io processor on a breadboard

Sent from my R1 HD using Tapatalk

[hamster_nz]

Here is a short answer, with millions of assumptions and no real thinking, but just on experience...

On low end FPGAs (Spartan, Artix, Cyclone, Zynq ... ) logically simple designs which do minimal work per cycle (not usually the simplest to design!) can run at more than 300MHz. Lots of pipelining and retiming involved.

Designs that utilise the FPGA's internal architecture features (e.g. us the DSP blocks properly) will run in the mid 200Mhz.

Without lots of work, a video processing pipelines will run at about 150 MHz. It is a big ask going to 300MHz for UHD resolution.

A well designed, moderately complex soft-CPU will clock at around 100 or 150 MHz.

[MK14]

Just checked out  http://www.analog.com/en/products/high-speed-logic/logic-devices/logic-gates.html
That have a range at 45 Gbps. This is good though I don't want to solder 1000's.
Any advice?
Thanks.

Why do you want such potentially huge speed ?
What exactly are you trying to achieve ?

The original Cray 1 supercomputer, is a good example, of perhaps the upper end of how fast a discrete component (limited to small scale logic ICs, ECL), computer might be able to run at.
But bear in mind it was designed by (probably) some of the best in the world computer experts, cost at the time $25,000,000 (much more in today's money) and needed a huge amount of electricity to power it. So much that it needed its own sub-power station.

All the above, gave it around 80 MHz clock speed (with each clock tick = 1 FLOP, with some rare exceptions, making it 2 rarely per clock cycle) (or 160 Million FLOPS peak, which did not apply for most tasks).

Whereas a $10 to $1,000 FPGA based cpu design can easily give you 100 MHz (maybe less) to 500 MHz MIPS (or FLOPS), and probably more than that. Depending on your budget and how competent you are at designing FPGA stuff.

I.e. discrete component cpu, is unlikely to exceed 100 MHz, for a complicated cpu.
But FPGAs can easily get to perhaps 500 MHz or more clock frequency, if the FPGA is of a fast enough type and your design is up to it.

[hamster_nz]

But FPGAs can easily get to perhaps 500 MHz or more clock frequency, if the FPGA is of a fast enough type and your design is up to it.

Oh, and another comparison...

As rough numbers, an Intel CPU core can do approximately 1 billion Multiply-Accumulate operations per second (1G MACS) per core (ignoring SIMD, SSE and so on...). With a US$3,500 E5-2698V4 with 20 cores that makes it 20G MACs peak performance.

I Also have a US$1342 XC7K325T-1FFG900C FPGA around 800 48-bit DSP blocks on it, and they can easily run at 250MHz. It can do 200 billion Multiply-Accumulate operations per second.

That makes it 10x quicker than a 20-core Intel Xeon, and 1/3rd the cost - as long as your algorithms map nicely into an FPGA datapath.

(prices from https://www.amazon.com/INTEL-PROCESSOR-E5-2698V4-2-2GHZ-SMART/dp/B01DTYQHTG and https://www.digikey.com/product-detail/en/xilinx-inc/XC7K325T-1FFG900C/122-1809-ND/2767546)

[joeqsmith]

I'm about to but a development kit but not sure which one but I'm looking at the MachXO 2280 Breakout Board http://uk.rs-online.com/web/p/programmable-logic-development-kits/7434788/

Can anyone tell me the speed of just 1 logic gate and the speed of 100 in series?
I have a great project in mind and any advice appreciated, I want the fastest.
Thanks

Paul.

Hey Paul, welcome to the forum.  Before you buy anything,  I would download some of the free tools and just get a feel without any hardware.  Don't get discouraged. 

I bought a Digilent ARTY board about a year ago to play with the new tools from Xilinx.  It was fairly inexpensive and came with a voucher for the license (really the reason I wanted it).   I setup the tools and went through the tutorials but I have not done anything with it beyond that.   It's pretty amazing what a $100 will get you now days.   

These videos show a few of my early home projects using FPGAs.   This first one shows some early FPGA prototyping boards I made. 


This video shows the larger card running. 


This video shows a couple of reverse print servers I designed.  These basically emulate a Centronics slave port and then dump the data to an Ethernet printer.   This was a pretty fun project.  I wrote the stack in assembler (a real dickhead move according to Dave).   


Good luck with your projects.

[hans]

Also don't pick a too small FPGA. Although some compact cores of a few hundred to maybe a 1000 LE's (Altera) exist, you want to have the extra space of a larger FPGA for routing, peripherals, debug stuff, etc.

Consider also the amount of block RAM available on the FPGA. Some FPGA's don't have ROM sections for program code, and so it needs to be stored in a block RAM. If you only got 16KB of memory, then that's not alot for code+data. Also note that programmers use kB for their firmware, and FPGA datasheets only talk about bits (as you can use block RAM often in data widths of e.g. 2-18 bits).

And yes, the purpose of softcores is purely academical or if you want to add custom peripherals or instructions. I used the NIOS softcore a couple of times on a Cyclone IV FPGA, and it can only run in the 50-100MHz range. The smallest CPU is quite compact, but it does not contain hardware integer multiply/divide. The bigger variants are faster, but a hard-silicon ARM Cortex m3 at same clockspeed will run circles around it.

Finally, if I were to write a softcore CPU myself (plan on doing that someday) I would probably clone an existing architecture so I can make use of their (GCC) compilers.

[chris_leyson]

If you're new to FPGAs and want to build a microprocessor you can learn a lot from this https://www.dc.uba.ar/materias/disfpga/2010/c2/descargas/TechXclusive%20Creating%20Embedded%20Microcontrollers.pdf Someone has taken the time to re-publish the Xilinx Tech Exclusive articles as a pdf "Creating Embedded Microcontrollers (Programmable State Machines)". It describes the Xilinx Picoblaze 8-bit microcontroller for Spartan3 FPGAs and there is even a version for the newer Spartan6 FPGAs. Be warned, the VHDL for the Picoblaze is a structural descripion using Xilinx primatives and not a behavioral description.
Then there is the Lattice Micro8, very similar to the Picoblaze but with several enhancements, it's also free so you could port it to other vendors silicon like Altera or Xilinx.
Do a bit of background reading and then you will get a better understanding of what FPGAs can and can't do efficiently.

[legacy]

the above picture is about a very simple 8 bit integer division implemented in fpga.

I can improve the algorithm to get the result in a shorter time but I have to pay more complexity and area, and the best result I can achieve with an integer division of 32bit  takes 35 clock cycles.

Not so bad, if we look at commercial ASIC solutions

- 41 clock cycles on AMD K7
- 50 clock cycles on Pentium 4 Netburst
- 29 clock cycles on Intel i7 Haswell

the real difference is
- how many LE does it take? a lot on fpga! ASIC uses less silicon
- which is the maximal frequency you can run the algorithm?

ISE v14.3 says @ 140Mhz on Spartan3E-500

[brucehoult]

If you're new to FPGAs and want to build a microprocessor you can learn a lot from this https://www.dc.uba.ar/materias/disfpga/2010/c2/descargas/TechXclusive%20Creating%20Embedded%20Microcontrollers.pdf Someone has taken the time to re-publish the Xilinx Tech Exclusive articles as a pdf "Creating Embedded Microcontrollers (Programmable State Machines)". It describes the Xilinx Picoblaze 8-bit microcontroller for Spartan3 FPGAs and there is even a version for the newer Spartan6 FPGAs. Be warned, the VHDL for the Picoblaze is a structural descripion using Xilinx primatives and not a behavioral description.
Then there is the Lattice Micro8, very similar to the Picoblaze but with several enhancements, it's also free so you could port it to other vendors silicon like Altera or Xilinx.
Do a bit of background reading and then you will get a better understanding of what FPGAs can and can't do efficiently.

Not a bad article, thanks.

I took delivery a week ago of my first FPGA board, an Arty Z7-20. It's probably got far more resources than I'll ever use with 53k 6-input LUTs, but you never know. It was only $50 more than the -10 with one third of the resources, and I had the $50. ($200 vs $150 vs $99 for original Arty without the ARM cores (which I may or may not end up using)

Primarily I want to play with different soft CPUs, ranging from historic ones to Linux-capable RISC-V or similar. However I've been busy with other things in the last week and didn't yet get Vivado to the point of being able to get a simple blinky or "press button, LED turns on" working yet.

[hans]

[..]

the above picture is about a very simple 8 bit integer division implemented in fpga.

I can improve the algorithm to get the result in a shorter time but I have to pay more complexity and area, and the best result I can achieve with an integer division of 32bit  takes 35 clock cycles.

Not so bad, if we look at commercial ASIC solutions

- 41 clock cycles on AMD K7
- 50 clock cycles on Pentium 4 Netburst
- 29 clock cycles on Intel i7 Haswell

the real difference is
- how many LE does it take? a lot on fpga! ASIC uses less silicon
- which is the maximal frequency you can run the algorithm?

ISE v14.3 says @ 140Mhz on Spartan3E-500

Also note that designing for FPGA's and ASIC's require slightly different strategies. In ASICs a flipflop is more expensive, in FPGA's you get them basically for free because if you're using the LUT the LE can also be configured to use the flip-flop (use or bypass).

Any project there is always the trade-off area, power and speed. You can basically implement multiply and division if you got an ALU than do (signed) add, subtract, shifts and some kind of immediate management. In last semester for a master college project we implemented a datapath that used the 'shift and add' multiply and long division. It worked out quite well, not perfect, watch out with those -128 * -128 multiplications  And same as you, it also took 35-40 cycles per operation to complete.

Just for kicks I did a straight multiply/divide in VHDL using 32-bit operands. I think it resulted in about 15k LE generated just for that operation. Whoops! I think our complete CPU only took like 3k LE, although that was still quite mediocre.

[suicidaleggroll]

I bought a Digilent ARTY board about a year ago to play with the new tools from Xilinx.  It was fairly inexpensive and came with a voucher for the license (really the reason I wanted it).

FYI - that voucher is pretty pointless.  All of the Xilinx Artix models are covered under the free Webpack license, which does basically everything Design Edition does:
https://www.xilinx.com/products/design-tools/vivado/vivado-webpack.html