Many thanks BuriedCode, I think I am beginning to at least understand where my holes of knowledge are.
No problem linking to appnotes, I have (tried) reading both of those, and generally prefer trying to figure them out, but at this stage I'm getting in a spin trying to understand what I need to implement from those.
I've attached the current stage of my component - I think I'm getting closer, but would like to verify a few things if possible. So I've got four 'interfaces', a clk, reset, Avalon_MM for signals I want to interface with the soft cpu, and conduit for signals in my module I want to connect to a pin out to the pcb.
In my avalon_slave_0_1, I have the two outputs from my module, which are of readdata types - so my cpu can read the data in the registers. Start is intended to control my verilog module, so a writedata would make sense to me here (I know it doesn't from the appnotes, but I can't figure out what would be better suited).
However, I still get the Signal readdata appears 2 times (only once is allowed). Presumably this is related to what you mentioned re addressing the registers? If so, how do I do this? I see the app notes refs addressing, but wouldn't that mean I'd have to alter my verilog to incorporate this?
Apologies for all the talk, and questions.
Thanks as always for your help. I think this will be a sudden 'aha' moment when it makes sense.