As I said, on reflection, I see exactly why it is done the way it is.
The counter is actually much simple than adder, and can be made much faster in general logic than using carry elements. FPGA doesn't have gates, but rather uses LUTs. 6-input LUT can calculate any bit of a 6-bit counter at once. This is faster than carry chains. If you use faster clocks you often can see your adders replaced with general logic. Also, some of the Xilinx's LUT may be configured into 32-bit shift registers which can cascade and replace short counters.
Xilinx allows two different levels of schematics - one is a simple schematics done from VHDL - called "elaborated design". Here you will see adders, muxes, gates etc. This is an abstraction of VHDL and has nothing to do with real FPGA.
Another level is post-synthesis schematics where you will see the elements of real FPGA - LUTs, DSPs etc.
These two are completely different schematics. It's important to know which one you're looking at.
Also you can look at the real FPGA map where you get the post-implementation view - all the elements of the FPGA are there, you can see which are used by the design and how they're connected together.