USB JTAG for FPGA Configuration

[electosleepy]

I've seen that the FT2232H is a popular IC for FPGA programming and debugging. The schematic for the Scarab miniSpartanr6+ for example uses one channel for JTAG and another channel for a FIFO interface described on page 41 of the FT2232H datasheet. Why would you choose FIFO over UART, I2C, or SPI. What is the FIFO channel responsible for? Is it used to write bitstreams to flash memory?

miniSpartan6+ schematic.
https://github.com/scarabhardware/miniSpartan6-plus/blob/master/miniSpartan6%2B_Rev_B.pdf

FT2232H webpage.
http://www.ftdichip.com/Products/ICs/FT2232H.html

FT2232H datasheet.
http://www.ftdichip.com/Support/Documents/DataSheets/ICs/DS_FT2232H.pdf

[baoshi]

These kind of application is usually meant for SPEED through USB2.0 port. FT2232H FIFO gives you full 480Mb/s throughput while SPI in sync mode only gives 30Mb/s

[electosleepy]

So once the FPGA is programmed through JTAG, I can transfer the bitstream data through the FIFO channel to the flash memory so it can reconfigure itself if the power is disconnected?