using 24 bit ADC IC MAX11201A with stm32

[basantab]

Hello
I am using Max11201A with stm32L100 discovery board. The problem is in datasheet it says 2 wire serial and just high on sclk gives 24 bit numbers.

Now in the datasheet the timings or schlk requirement is 5 MHZ which is a bit confusing to produce to me. When i toggle the pin high and low in without delay the duty cycle period is in microsecond . and with every 80 nanosecond pulse its going to shift out bits so to get 24 bit out i push 80 ns clk 24 times (rise and fall).

(i am relatively new to this stm32) :-)
Question
the question is how should i produce 80 ns spaced pulse(24 pulse) ?

(is it timer option i need to play with ?)

and also how to read those bits fast and knowing i read those bits in exact timing ?

thankyou for any inputs

[iMo]

The datasheet does not say the SCLK period is 80ns. It does say the MIN pulse width low and high is 80ns.
Simply set SCLK clock to something less than 5MHz and you will be fine.

and also how to read those bits fast and knowing i read those bits in exact timing ?

You do not need exact timing when below 5MHz clock. You may start with bitbanging the L100's SCLK output while reading DOUT. Add a small delay (ie 1us) when toggling the SCLK and when you learn how to read the 24bit of data you may optimize the reading to be faster speed.

[newbrain]

A (extended) couple of hints, the first ones that come to mind:

• 5MHz is the upper limit: as long as the SCLK frequency is lower than that, you are fine (no minimum given).
• The same goes for the 80ns, that's the minimum high or low duration for a clock pulse.
• Using SPI would be an easy solution, but the 25th and possibly 26th pulses complicate things a lot (could still be possible...).
• Every bit is shifted out at most 40ns after a positive clock edge, but no less than 3ns.
• This allows you to generate a clock pulse (__--__) and then read the bit, without worrying about the exact timing: just generate the new one after you are done reading.

[basantab]

thanks for taking time to reply


i basically created sclk 24 pulse of 200ms but result is always high in corresponding output regardless of what voltage vlaue i put. I have basically tied vref positive to vcc and vref negative to gnd and negative input is gnd and positive input is changed with pot....

on top of that when ever the clock is low (200ms) i get around 22 small peaks(or probably 24 if counted edges)(although in picture there are 4 or 5 peaks when used different sampling time it appears around 24) which is 160us(in data sheet it is said next data time and no read)  and after that 8.6 ms low(data conversion time) and again that peak 160us).

i thought it was simple just push one clock and i get first msb data (24th bit) and push another pulse i get another bit of data(23rd msb)...... unitll that last 24th bit which gives me lsb(1st bit).

things looks a bit different here.

is it circuit arrangement a mistake as it is differential input ?

thankyou again everyone for taking time to see this.

[iMo]

Your ADC shoots the data out with 120 samples per second automatically. Therefore you see a lot of pulses (RDY) there spaced around 8-9ms.

The  output rate  is  predetermined  based  on  the  package  option (MAX11201A at 120sps and MAX11201B at 13.75sps).

You have to read the datasheet:

The RDY/DOUT is used to signal data ready, as well as reading  the  data  out  when  SCLK  pulses  are  applied. RDY/DOUT  is  high  by  default.  The  MAX11201 pulls RDY/DOUT low when data is available at the end of conversion,  and  stays  low  until  clock  pulses  are  applied  at the SCLK input. On applying the clock pulses at SCLK, the RDY/DOUT  outputs  the  conversion  data  on  every SCLK  positive  edge. 
To  monitor  data  availability,  pull RDY/DOUT high after reading the 24 bits of data by supplying a 25th SCLK pulse.

You have to poll the RDY, when it goes low (data ready) you have to clock in the SCLK and you get the data out. With 25th pulse you set the RDY to high, and again, wait for the next data ready by polling the RDY (for example - in a "while{}" loop wait until RDY is low, or, use an interrupt triggered by the falling RDY edge).

Your SCLK "period" cannot be longer than 300us (reading all the data bits must fit into 1/120sps), I guess. Use HAL_Delay_Microseconds, for example 10us in your code above, to be on the safe side..

Pseudo code, for example:

Code: [Select]

set SCLK = 0;
data = 0;
while ((read RDY) == 1) {};      // wait on RDY == 0
for (i=0;i<24;i++) {       // read 24bits, MSB first
  data = data << 1;
  set SCLK = 1;            // data from DOUT on rising edge
  delay 10us;
  data = data + (read RDY);
  set SCLK = 0;
  delay 10us;
  }
set SCLK = 1;              // set RDY to 1 with 25th SCLK
delay 10us;
set SCLK = 0; 
delay 10us;