Using YMF262 without YAC512 - is it feasible?

[technix]

I found someone selling YMF262 for cheap, and my retrocomputers need sound. The same shop also carries YAC512 but at a higher price, and most of my modern chips uses I2S for digital sound instead of that float point signal. I would want to build something in place of that YAC512, converting the 49.7ksps quad-channel floating point audio into a 48ksps 24-bit integer quad channel I2S without leaving the digital domain for maximum sound quality preservation.

I wonder what is the most appropriate chip for this task: a FPGA/CPLD like XC6SLX9, a microcontroller like STM32F722, or a DSP like ADSP-BF531?

This is needed on my 8088 retrocomputer project as that thing has a FlexCGA graphics card that outputs RGBI natively. My plan for that is to convertits RGBI into RGB888 using a CPLD and shoot that signal out over HDMI. Having YMF262 on there with this data conversion means I can send the audio along with the video at no loss of quality, all staying within the digital domain for lossless conversion and transmission. Also if it is appropriate to use FPGA for this data conversion both the YMF262-to-I2S and RGBI-to-RGB888 can be done on one FPGA chip.

p.s. Someone is selling MOS6581 SID for 5 dollars each. Too bad that chip is an analog-only one...

[beyon]

I thought about doing something similar a few years ago but for the ym2151.

Should have a schematic somewhere for a solution I came up with but haven't implemented yet(?).

The idea in any case was to input the serial data output from the ym2151 into serial-in/parallel-out shift registers and the sample/hold outputs connected to some logic chips to signal when one sample is fully loaded into the shift registers and one bit to signal which channel it was.

A micro-controller would then use a input pin change interrupt on the pin connected to the "one sample fully loaded" signal which would trigger a routine to read the parallel data from the shift registers plus channel indicator bit.

By turning the serial data into parallel the rate the  micro-controller has to read it's input is lowered.

The sound chip would be fed the I2S clock instead of it's usual clock. This will of course make the chip produce slightly out of tune notes unless corrected by software.

As I said I haven't test the idea yet but it should be able to work and it should be similar for the ymf262 although the outputs intended for the DAC might be slightly different and you'd have two more channels to handle.

[tsman]

Try talking to this person about it https://www.vogons.org/viewtopic.php?f=62&t=63110 They're using an old Terasic DE1 board so their implementation is Altera based and fits inside a Cyclone II 2C20 which has 20K LEs.

[Rasz]

tsman post reminded me I saw a similar project few years ago, but using Cypress FX2LP USB bridge chip to sample serial output, it was something about comparing quality between yamaha FM clones maybe?

hmmm searching ...
or maybe it was just part of an effort to emulate OPL3 I read about at http://forums.submarine.org.uk/phpBB/viewforum.php?f=9
something to do with https://github.com/gtaylormb/opl3_fpga

[technix]

tsman post reminded me I saw a similar project few years ago, but using Cypress FX2LP USB bridge chip to sample serial output, it was something about comparing quality between yamaha FM clones maybe?

hmmm searching ...
or maybe it was just part of an effort to emulate OPL3 I read about at http://forums.submarine.org.uk/phpBB/viewforum.php?f=9
something to do with https://github.com/gtaylormb/opl3_fpga

I have already bought samples of OPL3 at 20 US cents each here, and the level shifting required is also a lot less for real OPL3.

The most headache-y thing for me here is downsampling from 49.7kHz to 48kHz. Running the clock slower to match the 48kHz sampling rate would make the music 4 cents flat, and require a strange input clock speed. I am already using a slightly faster core clock at up to 16MHz with the NEC V20 on my 8088 project.