Hi all,
I've been trying to implement a RS232 transmitter, following the example at
http://www.fpga4fun.com/SerialInterface3.html, however I have run into a problem and cannot seem to figure out what I am not considering.
Aside from following through the tutorial, I've added my own tick at around 1400Hz to enable the Tx to start, and I suspect this might be causing the fault, but after trying to see why I cannot. My Verilog is as below:
//module input and output,
module RS232Link(clk, TxD);
input clk; //48MHz
output TxD; //UART
//Baud tick (for 115200)
reg[18:0] acc;
always @(posedge clk)
acc <= acc[17:0] + 629;
wire BaudTick = acc[18];
//Transmission start control (1400Hz)
reg[15:0] startacc;
always @(posedge clk)
startacc <= startacc[14:0] +1;
wire TxD_Start = startacc[15];
//Bit order
reg[3:0] state;
always @(posedge clk)
case(state)
4'b0000: if(TxD_Start) state <= 4'b0100;
4'b0100: if(BaudTick) state <= 4'b1000; //start bit
4'b1000: if(BaudTick) state <= 4'b1001; //bit 0
4'b1001: if(BaudTick) state <= 4'b1010; //bit 1
4'b1010: if(BaudTick) state <= 4'b1011; //bit 2
4'b1011: if(BaudTick) state <= 4'b1100; //bit 3
4'b1100: if(BaudTick) state <= 4'b1101; //bit 4
4'b1101: if(BaudTick) state <= 4'b1110; //bit 5
4'b1110: if(BaudTick) state <= 4'b1111; //bit 6
4'b1111: if(BaudTick) state <= 4'b0001; //bit 7
4'b0001: if(BaudTick) state <= 4'b0010; //stop 1
4'b0010: if(BaudTick) state <= 4'b0000; //stop 2
default: if(BaudTick) state <= 4'b0000;
endcase
//Data serialisation
reg muxbit;
reg[7:0] TxD_data;
assign TxD_data = 69;
always @(state[2:0])
case(state[2:0])
0: muxbit <= TxD_data[0];
1: muxbit <= TxD_data[1];
2: muxbit <= TxD_data[2];
3: muxbit <= TxD_data[3];
4: muxbit <= TxD_data[4];
5: muxbit <= TxD_data[5];
6: muxbit <= TxD_data[6];
7: muxbit <= TxD_data[7];
endcase
//output
assign TxD = (state<4)|(state[3] & muxbit);
endmodule
And here is an example of the RS232 frames I have captured, some start bits are as short as 1.6us.
Again, I think the problem might be my start tick implementation, but I am likely to be wrong about that too.
Any advice or suggestions would be appreciated.