Verilog, Vivado post synthesis simulation does not work

[gauravmp]

Hi,

I've done a simulation before synthesis and it works just fine. I ran a synthesis and implementation and then run good with a few warnings. However, when I ran a post synthesis simulation, it gives a different waveform, something which i did not expect.

Could someone please tell me how I could find my errors?

Thanks

[Kilrah]

How do you expect help with absolutely zero information? 

Give as many details as you can about what you're trying to do, what you're getting, what you're not getting, what you're expecting to get...

[Sal Ammoniac]

I assume the simulation that works is a behavioral simulation? That type of simulation does not take into account any synthesizer optimizations performed or any timing considerations.

When you run a post-synthesis or post-implementation functional simulation the simulator does take into account any optimizations made to your design during the synthesis and/or implementation steps. The synthesizer may have, for example, optimized away a part of your design that in turn causes the simulation to behave differently.

Behavioral simulations assume that propagation delays and setup/hold times are zero. Timing simulations do not, and if your design is wonky a timing simulation probably won't look like a behavioral simulation either.

I suggest you read the document titled Vivado Design Suite User Guide - Logic Simulation. It covers all these things.

[gauravmp]

Thanks! I figured that I had multiple drivers which was messing up my code