There are some on line courses. They are quite basic, but very useful.
Here there is one from asic world:
http://www.asic-world.com/verilog/index.html.
I'd recommend you get yourself acquainted with a simulator like icarus verilog (
http://iverilog.icarus.com), you can also use the ones that come with Xilinx' WebISE/Vivado or Lattice Diamond (Aldec HDL). Do the examples and code there, and remember (almost) everything happens in parallel
, Verilog and VHDL describe circuits with gates and flip-flops.
Note: I haven't looked at your VGA example but from what I have done I know that you can easily construct a (simple) VGA controller using counters, comparators and gates, and an oscillator. Try a circuit for the horizontal sync. A counter, 3 comparators, few gates and an oscillator... there is nothing more to it.
module hsync(
input wire clk_25,
output reg hsync
);
reg [9:0] hreg;
always @(posedge clk_25)
begin
if (hreg < 10'd800)
hreg <= hreg + 10'd1;
else
begin
hreg <= 10'd0;
end
hsync <= (hreg < 96) ? 1'b0:1'b1;
end
endmodule
There you have a counter
hreg, two comparators:
(hreg < 96) and
(hreg < 10'd800), and I used an extra flip-flop for the sync signal
hsync.
How does it work ?
Well, the horizontal synchronism signal is a periodic signal, it has a low part (sync active) and a high part (no sync inactive) (for VGA 640x480 @ 60 Hz). The low part are some 96 clocks @ 25 MHz, aka 96 pixels. Visible pixels are 640... the rest are what is know as front porch (before visible part) and back porch (after visible part).
There are several ways of achieving such a signal. The code above is one of those.
vertical sync is generated in a similar manner but the timing is different
.
have fun !
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