You're absolutely right to take the warnings seriously. They may not matter for a relatively trivial design, but understanding and eliminating them now will definitely get you into good habits which will be more important as your projects grow in complexity.
Don't use multiple clock domains unless you need to. In this case, using clk_50 as your one and only clock is absolutely the right thing to do.
If you have multiple clocks, then you need to be very sure you understand the timing relationship between them. It's not unusual for the synthesis tool to have to include a lot of routing delay (== wasted logic space) just to ensure that the actual behaviour of the circuit is in accordance with your VHDL source. For example, suppose you have logic along the lines of:
- on clock A, read some inputs, and assign a new value to signal B. Also, under some conditions, generate a rising edge on clock C.
- on clock C, read the value of signal B and generate output D
This is a problem, because things have to happen in a strict order:
- B and C depend on A
- D depends on the new, updated value of B
There's a problem if calculating the new value of signal B takes longer than calculating the new value of C. Signal (clock) C must be delayed for at least as long as it takes for the new value B to become valid, so that D is generated correctly. This means sending it up, down and across the chip just to waste time.
It's much better, therefore, to have everything depend on one clock, even if the logic is more complex.
The right thing to do in this case, is to retain the previous state of 'bothbut', and (in the clk_50 domain) to check whether the current value is '1' and the previous, stored value was '0'.