VHDL - How to test with IF only a subset of bits in a std_logic_vector

[alank2]

I am trying:

signal recv_data : std_logic_vector(31 downto 0);


if (recv_data(7 downto 0) = "00000001") then

Fails - probably be specifying it wrong - can this be done?

[AndyC_772]

Yes, it can, and your syntax looks fine. Your problem is elsewhere.

[alank2]

Are you sure?

I found the alias command that allowed me to do this and it does not error:

alias recv_data_7d0 is recv_data(7 downto 0);

Then this line does NOT error:

if (recv_data_7d0 = "00000001") then

Thanks!

[AndyC_772]

Yes, absolutely sure

What happens if you remove the extraneous brackets, ie.

Code: [Select]

if recv_data(7 downto 0) = "00000001" then

[alank2]

Now it is working!  Wow, I am pretty sure I cut/paste that instruction in the first post directly from it.  I must have had something else wrong.