VHDL. this signal is connected to multiple drivers. Help me please TODAY!!!

[timgep]

I have main entity for example.

I also have RAM 16*8bit component. Which has port (address, accessing indicator, reading indicator, writing indicator, IN/OUT DATA)

So, first 16 clock cycles I need to read main's entity input (byte_input). And send it to RAM component.

From 16 to 32 clock cycles, I have to read data from RAM, process it and rewrite again to ram component from 32 to 48 clock cycles.

But I stalled in the first part. I can't even read entity's input and send it to the RAM. When synthesizing it says "Multi-source in Unit <top_module> on signal <ram_data<2>>; this signal is connected to multiple drivers"  

Code:

Code: [Select]

PROCESS(clk)
BEGIN
if(rising_edge(Clk)) then
if (cnt>=0 and cnt<16) then
ram_data<=byte_input;
end if;
end if;
end process;

gate_1: ram16x8 port map(address=>ram_address,csbar=>'0',oebar=>'0',webar=>ram_webar,data=>ram_data);

[mikeselectricstuff]

Everything that drives the RAM address lines must be assigned within the same process.

You should probably also be using dual-port RAM to make things simpler

[timgep]

Everything that drives the RAM address lines must be assigned within the same process.

You should probably also be using dual-port RAM to make things simpler

I put everything in one process as you said. But problem did not disappear.

Could you please correct me if I am wrong. I have some doubts that I can use component and process in one entity. Should I separate them? (but it is harder to control ram within other entity)

[timgep]

gate_1: ram16x8 port map(address=>ram_address,csbar=>'0',oebar=>'0',webar=>ram_webar,data=>byte_input);

When I changed data pointer directly to byte_input, it was possible to synthesize.

But I need somehow to control when and what I am sending in to RAM

Also I found another mistake with previous case:

Code: [Select]

Hierarchical block <gate_1> is unconnected in block <top_module>. It will be removed from the design.

[Scrts]

You have to use tristate (which MUST be instantiated in the top module) and control tristates OE signal.