Author Topic: VHDL Tools ?  (Read 7921 times)

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Offline tjaTopic starter

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VHDL Tools ?
« on: August 10, 2017, 02:23:22 pm »
I am trying to learn VHDL, specifically in a Xilinx ISE / Spartan 6 environment. Am I missing something here, or is it horrendously difficult to understand existing VHDL projects?
I have generated code to access DDR2 memory using the Xilinx MIG, and I am trying to understand the example design. In a project written in a mainstream language (C for example) I'd expect to be able to generate some form of structure diagram (what calls what etc), a cross reference listing, showing what variables are accessed by what modules and so on. These types of reports are incredibly useful when you are trying to get your head around an unknown codebase.
As I say, unless I'm missing something, it is not possible to obtain this type of information for a VHDL codebase (and I realise that one cant compare exactly languages like C and VHDL, but the principle of using tools to analyse and cross reference etc still applies).

So, experienced VHDL hackers out there, when faced with understanding a new VHDL codebase of non-trivial size (>2000 LOC), what process / tools / magical incantations would you use?

Cheers

Tim
 

Offline legacy

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Re: VHDL Tools ?
« Reply #1 on: August 10, 2017, 03:17:02 pm »
is it horrendously difficult to understand existing VHDL projects?

If you start with complex projects ...
DDR-ish is assumed "advanced".
 

Offline legacy

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Re: VHDL Tools ?
« Reply #2 on: August 10, 2017, 03:25:45 pm »
I'd expect to be able to generate some form of structure diagram

like Scitools dot com Understand (C/C++) ?

compare exactly languages like C and VHDL

Sigasi helps you to write your code, but it's like Eclipse (autocomplete, hashing, ...).
It's not like SciTools-Understand. If that was your question.

I mean ModelSim is *THE* tool. You can integrate it inside ISE.
Never tried on Vivado.
 

Offline stmdude

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Re: VHDL Tools ?
« Reply #3 on: August 10, 2017, 04:39:04 pm »
Even if you start with a _much_ simpler design than a DDR-controller, (in my experience) you'll have issues reading other peoples code.

First off, call-graphs and static analysis doesn't really makes sense in an HDL context, as everything is concurrent. There's no calls, functions etc...

Also, HDL languages seem to have gotten stuck somewhere in the 80s. None of the modern niceties of a modern language is present. No namespaces, structs, etc.  All of this is implementable in a HDL (as it has no bearing on the outputted code), but it makes it _much_, _much_ easier to organize ones code and make it more readable.

Since it pretty much is impossible to write clean and understandable HDL once you get up to scale, understanding other peoples projects will be difficult.

In the end, I pretty much adapted the strategy "I'll write something just like this module, and I'll copy the sh*t of out of it" (copyrights be damned). Once I got along a bit, I started to understand the original much better, and I could discontinue my own version, and use the original instead..
 

Offline nctnico

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Re: VHDL Tools ?
« Reply #4 on: August 10, 2017, 07:15:00 pm »
Even if you start with a _much_ simpler design than a DDR-controller, (in my experience) you'll have issues reading other peoples code.

First off, call-graphs and static analysis doesn't really makes sense in an HDL context, as everything is concurrent. There's no calls, functions etc...

Also, HDL languages seem to have gotten stuck somewhere in the 80s. None of the modern niceties of a modern language is present. No namespaces, structs, etc.  All of this is implementable in a HDL (as it has no bearing on the outputted code), but it makes it _much_, _much_ easier to organize ones code and make it more readable.
I guess you missed VHDL which can do all that!
More on topic: there is Sigasi (both standalone and Eclipse plugin) but they only offer a node locked subscription model. For Eclipse there is also the free/open source Veditor plugin which helps to deal with large VHDL projects.
There are small lies, big lies and then there is what is on the screen of your oscilloscope.
 

Offline tjaTopic starter

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Re: VHDL Tools ?
« Reply #5 on: August 10, 2017, 08:48:17 pm »
While VHDL executes concurrently, the source code is still structured (or can be structured) in a nested (for want of a better word) fashion, and some kind of structure diagram still makes sense if you are trying to make sense of a large codebase. The DDR example I am trying to understand is nested at least 6 deep (as in component instantiations).

Stuck in the 80's? Totally agree. While the hardware maybe moving forward in leaps and bounds, the software is decades behind - or at least the Xilinx stuff. (Newer VHDL standards may be more capable, but don't tell me - tell Xilinx). And decades behind in terms of the most basic best practice - formatting, naming standards, comments|O

Haven't tried Sigasi - looks like all the best features are paid for, but I ought to at least try the free version. Certainly looks the most professional VHDL specific offering.

Couldn't get veditor to install on my Eclipse (Mars) - looks like they haven't kept up with the latest installations standards.

Tried SVeditor (IIRC) - totally oriented towards System Verilog (as the name suggests!) - VHDL functionality is very basic.

I have resorted to rolling my own Python regular expression code (heavily based on VHDL Analyser) to provide some (pretty crude) cross ref and structure analysis, which is helping me understand this code base.
 

Offline NorthGuy

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Re: VHDL Tools ?
« Reply #6 on: August 10, 2017, 09:07:26 pm »
... and some kind of structure diagram still makes sense if you are trying to make sense of a large codebase.

I guess that would be schematics.
 

Offline hamster_nz

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Re: VHDL Tools ?
« Reply #7 on: August 10, 2017, 09:21:19 pm »
Everybody loves to blame the tools, but IMO difficulty to understand behavioral HDL is an inherent problem.

(single-threaded) Procedural code tells a story, and has relatively isolated context - you can look at small bits in isolation, and you know exactly what is going on, and how it achieves its result. And you can also make a whole lot of assumptions too - however with SMP or parallel systems (or even signals and interrupts) it can get a little more complex quite quickly.

HDL code is the blueprint for a machine, and like any other machine, a machine made of simple bits. If I hand you an cog from an automatic transmission and ask "what exactly does this do?" it is a very hard question to answer (unless you are a transmission expert). You know it is a cog, and it might be 200mm and have 50 teeth, but to understand what it does and how it does it relies on context and the fine detail of its iteration with other parts in the system.

If it isn't a standard design pattern that you recognize (f.e. "oh that is the idler thrust plate switcher cog") , or you can't find enough documentation (e.g. comments in VHDL) then you really need to watch it in action to see how it works - hence why simulating HDL modules is usually required for understanding in tricky cases.

As you get to the higher levels it tends to get easier to put everything in context, as you work at a more structural level - just as understanding how a car works is far easier than an automatic transmission works.
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Offline agehall

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Re: VHDL Tools ?
« Reply #8 on: August 11, 2017, 04:48:49 am »
@tja - you are thinking too much in terms of software. HDLs is not software, it's hardware. The sooner you stop thinking of it in terms of software, the sooner you'll understand it.
 

Offline dgtl

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Re: VHDL Tools ?
« Reply #9 on: August 11, 2017, 05:28:24 pm »
Vivado has a very good schematics viewer. After synthesis or implementation, you can visualize the results. You can start from whatever node in structure and go from there: select some signal in the structure list and press f4 (afaik it was in right-click menu, too). The schematics viewer shows only that node up to the hierarchy boundary. When double-clicking the interface at the boundary, the view is expanded (double click on the side you want to expand to). This is a very powerful feature to track down signals in very large projects and to verify that the synthesizer understood the code the same way you intended to write it (I always write code by thinking at the synthesis result and then later verify that it matches). In case of targeting very high clock frequencies, the result must be considered while writing the code. For Xilinx 7-series, you have to understood the details about 6-LUTs and then try to pipeline the code to fit in usually 1 LUT between registers and worst case 2 LUTs to reach the highest clock frequencies possible for the chip. For a large component, it gets quite tricky (my last work is a massively parallel 25-stage pipelined module having >10k LUT, a lot of blockram and distram and has to run at 300MHz for Artix7 -1 speed grade).

I'm using SVEditor for editing my SystemVerilog sources on Eclipse Neon (Linux host). I have used veditor and it did work on Eclipse Neon, but when by mistage a systemverilog file was opened with it and it saw systemverilog syntax (x='{default:'1}), it crapped out so terribly, that eclipse needed a restart - so it is currently uninstalled on my machine.

SystemVerilog has evolved a lot compared to old verilog, but the support on Vivado is terribly buggy. In the last month, I've met a bunch of cases where synthesis just segfaults. Also there are corner cases, where either Vivado synthesis or simulator misunderstands the code and creates something stupid. Sometimes one of them handles things correctly and the other messes up and sometimes vice versa. So a lot of time is spent on tracking down Vivado bugs and then working around them. For systemverilog, the things to avoid are streaming operator (pack/unpack) and +: and -: indexing of arrays. Also it is good to use a lot of intermediate signals as the tools tend to mess up when a lot of different operations are on one line.
 

Offline rstofer

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Re: VHDL Tools ?
« Reply #10 on: August 11, 2017, 09:00:04 pm »
I don't think I would start my VHDL career with MIG and DDR<anything>.  Like everything else in life, you have to crawl before you walk before you run.

Blinking an LED is trivial but it does prove that the toolchain, board and user are all on the same page.

Go through a VHDL book that discusses what I think of as 'patterns'.  There is a pattern for describing just about everything.  Gates, registers, decoders, multiplexers, priority trees and finite state machines.  Given these building blocks, design something.  Maybe a simple CPU - nothing major, perhaps an elementary machine like BLUE (Computer Architecture - Caxton C Foster 1971).  This machine can be built without an FSA because it uses a LOT of timing slots.  It also uses a bus architecture (open collector type stuff) and you may want to omit that and use a MUX where appropriate.

Once you have written several thousand lines of code and gotten a couple of projects running, come back to the MIG project and see what you think.  I always have trouble reading other people's code and when I see 90% of code is variable assignments and not signals, I know I am out of my league.  Same with Verilog - I just don't quite 'get it'.  Probably because I have never spent the time to learn.  I started with VHDL and that is where I'll stay.

Seriously, it's all about 'patterns'.  You look at an FSA and you immediately know how it's going to work.  It may have 100+ states spread over pages and pages of code but it still fits the 'pattern'.
 

Offline julian1

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Re: VHDL Tools ?
« Reply #11 on: August 12, 2017, 12:37:20 am »
Never tried them, but some alternatives are, 

  - Chisel which is embedded in scala https://chisel.eecs.berkeley.edu/
  - Bluespec proprietary, apparently similar to Haskell https://en.wikipedia.org/wiki/Bluespec
  - Clash, functional/haskell inspired, http://www.clash-lang.org/

They synthesize/generate a verilog/vhdl target, in order to interoperate with a hardware vendor's tools.

 
 

Offline mac.6

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Re: VHDL Tools ?
« Reply #12 on: August 13, 2017, 06:46:33 pm »
There is also spinalHDL, quite close to chisel but with nice differences.
 

Offline rstofer

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Re: VHDL Tools ?
« Reply #13 on: August 13, 2017, 07:42:37 pm »
So, if I were to go somewhere and get a job working with FPGAs, which tools would I be compelled to use?  I'd be willing to bet it will be one of the main vendor tools.  None of the obscure tools are going to be used in industry.

With that thought in mind, I would look at the Xilinx, Altera and Lattice toolchains and leave all the other stuff for the academics.

Beyond synthesis and simulation, tools need a detailed understanding of the FPGA fabric and the vendors aren't going to supply it for IP reasons.  Place and route is certainly chip specific and with more complex chips, the logic of P&R gets even more difficult.  Even the pin IO structure is complicated and not at all standardized.

Here is an interesting article that delves into why there aren't going to be any non-vendor toolchains in use:

http://www.eejournal.com/article/20161004-opensource/

Just be happy that there are free versions of the vendor tools.  Sure, they're limited, but they get you started and are quite capable of creating fairly large projects.


 

Offline nctnico

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Re: VHDL Tools ?
« Reply #14 on: August 13, 2017, 07:59:56 pm »
So, if I were to go somewhere and get a job working with FPGAs, which tools would I be compelled to use?  I'd be willing to bet it will be one of the main vendor tools.  None of the obscure tools are going to be used in industry.

With that thought in mind, I would look at the Xilinx, Altera and Lattice toolchains and leave all the other stuff for the academics.
You have to split between doing the synthesis, p&r etc and editing / managing HDL. Editing / managing HDL is better left to IDEs which specialise in that. In case of Xilinx you can do use ISE only for the synthesis etc bit or even do entirely without ISE and use makefiles / scripts for the build process. Personally I'm using Eclipse + veditor to edit/manage VHDL and only use ISE for the synthesis etc.
There are small lies, big lies and then there is what is on the screen of your oscilloscope.
 

Offline legacy

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Re: VHDL Tools ?
« Reply #15 on: August 13, 2017, 08:53:05 pm »
open source FPGA code will be difficult for all the reasons pointed out in this article

no mater anyway
 

Offline legacy

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Re: VHDL Tools ?
« Reply #16 on: August 13, 2017, 08:54:44 pm »
use makefiles / scripts

Modelsim scripts here  :D
 

Offline legacy

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Re: VHDL Tools ?
« Reply #17 on: August 13, 2017, 11:20:38 pm »
What is annoying is that, according to VHDL specification, the predefined attribute e.g. 'left can be applied to integer type, but apparently this isn't supported by some synthesis tools and simulators.

In Xilinx ISE webpack is not supported  :palm: :palm: :palm:
 

Offline legacy

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Re: VHDL Tools ?
« Reply #18 on: August 13, 2017, 11:23:31 pm »
Code: [Select]
  constant counter0_right    : integer := 15;       
  constant counter1_right    : integer := 7; 
  signal counter0            : integer range 0 to counter0_right:=0;   
  signal counter1            : integer range 0 to counter1_right:=0;

...
    elsif rising_edge(in_clock) then     
        if (counter1 < counter1_right) then
          counter1   <= counter1 +1;
        else
...

have to work around it
 

Offline nctnico

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Re: VHDL Tools ?
« Reply #19 on: August 13, 2017, 11:26:01 pm »
I guess the problem is that the number of bits of an integer is undefined so the signal cannot be translated to real hardware.
There are small lies, big lies and then there is what is on the screen of your oscilloscope.
 

Offline hamster_nz

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Re: VHDL Tools ?
« Reply #20 on: August 14, 2017, 12:06:20 am »
What is annoying is that, according to VHDL specification, the predefined attribute e.g. 'left can be applied to integer type, but apparently this isn't supported by some synthesis tools and simulators.

In Xilinx ISE webpack is not supported  :palm: :palm: :palm:

X'high      The upper bound of X
X'low      The lower bound of X
X'left      The leftmost bound of X
X'right      The rightmost bound of X

Does the idea of 'leftmost' and 'rightmost' apply to integer's range? I guess it should, but depends on 'to' or 'downto' being used in the range....

Maybe 'high' and 'low' will work as desired?
« Last Edit: August 14, 2017, 12:09:52 am by hamster_nz »
Gaze not into the abyss, lest you become recognized as an abyss domain expert, and they expect you keep gazing into the damn thing.
 

Offline legacy

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Re: VHDL Tools ?
« Reply #21 on: August 14, 2017, 12:53:46 am »
X'high      The upper bound of X
X'low      The lower bound of X
X'left      The leftmost bound of X
X'right      The rightmost bound of X

Modelsim says it's OK, it accepts the code and the simulation goes fine
ISE claims that object prefix must be an array, which is not correct according to vhdl definition

If you define something as integer, no matter if you resize the range, types all come with a left and right border.
 

Offline legacy

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Re: VHDL Tools ?
« Reply #22 on: August 14, 2017, 12:56:14 am »
number of bits of an integer

number of bits has nothing to deal with a language type's range.

 

Offline legacy

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Re: VHDL Tools ?
« Reply #23 on: August 14, 2017, 01:13:02 am »
Code: [Select]
subtype col_t is std_logic_vector(number_of_cols-1 downto 0);

function get_ones_in_column(inp: col_t)
...
for i in inp'range loop
...

this works as expected on both ISE and Modelsim, anyway  :-//
 

Offline NorthGuy

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Re: VHDL Tools ?
« Reply #24 on: August 14, 2017, 05:01:55 am »
Here is an interesting article that delves into why there aren't going to be any non-vendor toolchains in use:

http://www.eejournal.com/article/20161004-opensource/

I think it's much simpler. There's no demand for non-vendor tools. If there was a demand, it wouldn't be so difficult to reverse-engineer bitstreams, gather timing information etc. p&r algorithms are rather straightforward and there must be simple open-source implementations already if you search well.

But, people seem to be content with vendor-provided tools. Vivado is bloated, slow, and buggy. However, people do not revolt. They rather perceive that Vivado deals with tasks of enormous complexity and therefore it is understandable that it takes long time for synthesis and/or p&r. No need for anything else.

 


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