Hello there, it's my first time posting here so I am not 100% sure if I chose the right category.
My problem is FPGA synthesis related. While simulations seem to work fine, when i try to synthesize my code i get the following error.
Code:
[Select][Synth 8-5765] size mismatch in assignment; read failed
which is associated with the reading code I have.
Code:
[Select] read(inline, dataread1);[\code] to be specific
Some parts of the code are below.
Code: [Select]library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.system_definitions.all;
use STD.textio.all;
.........
process(clk,reset)
file infile : text;
variable inline : line;
variable dataread1 : asobel_int_internal;
begin
......
elsif reset = '0' then
if (not endfile(infile)) then
readline(infile, inline);
read(inline, dataread1);
data_in <= dataread1;
Asobel_int_internal is a -2^10 to 2^10 integer declared in the system_definitions package.
Any idea how to fix this ?
Thanks in advance