what does always@(*) do

[gauravmp]

Hi,

Could someone tell me what always@(*) do? Is the always block executed everytime there is a change in any of the variables?

THanks

[kfnight]

Pretty much. Once upon a time Verilog required a sensitivity list. When any of the signals in the sensitivity list changed value then the simulator would descend into the always block.

Code: [Select]

reg a;

always @(b, c)
begin
  if (b)
    a = 1'b1;
  else if (c)
    a = 1'b0;
  else
    a = 1'b0;
end

Engineers found this annoying since the simulator or synthesis tool should be able to infer the sensitivity list by analyzing the signals in the always block during compilation. So the always @(*) construct was introduced, saving engineers a few keystrokes, and saving a lot of hours debugging the design due to a missing signal in the sensitivity list.

Code: [Select]

reg a;

always @(*)
begin
  if (b)
    a = 1'b1;
  else if (c)
    a = 1'b0;
  else
    a = 1'b0;
end


[photon]

An issue caused by the old style sensitivity list was that the synthesizer would make a latch for any missing signal from the sensitivity list. Since an always block without a clock is intended for combinational logic, this added latch would be a bug. The new syntax always @(*) prevents this.

[gauravmp]

Thanks guys!