Author Topic: SOLVED (ish): layout goof: Can I use 3.3V instead of 2.5V for MAX10 LVDS inputs?  (Read 3141 times)

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Offline aandrewTopic starter

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This is one of those dumb mistakes that made it through review.  |O

Altera MAX10M08DAF, I have a number of LVDS inputs on banks 5 and 6. I connected the VCCIO for these banks to 3.3V and not 2.5V as is specified in the manual.

This is a BGA device and it's going to be a royal PITA to repair this, but I'm literally a day or two out from the parts being populated on the errored boards so if it needs to be fixed, this is the best time to do it.

My question is how bad of a screwup is this? The LVDS signals are all inputs to the FPGA, and the maximum clock frequency will be 125MHz, and some of those LVDS signals are DDR, so the bit rate on some of those LVDS signals will be 250Mbps.

Will I get a "hail mary" pass by virtue of this being a receive-only interface, or should I bite the bullet, halt assembly of these prototypes and try to rework the 7 balls (buried inside the array of course) so they receive 2.5V?
« Last Edit: January 30, 2019, 02:52:47 am by aandrew »
 

Offline langwadt

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This is one of those dumb mistakes that made it through review.  |O

Altera MAX10M08DAF, I have a number of LVDS inputs on banks 5 and 6. I connected the VCCIO for these banks to 3.3V and not 2.5V as is specified in the manual.

This is a BGA device and it's going to be a royal PITA to repair this, but I'm literally a day or two out from the parts being populated on the errored boards so if it needs to be fixed, this is the best time to do it.

My question is how bad of a screwup is this? The LVDS signals are all inputs to the FPGA, and the maximum clock frequency will be 125MHz, and some of those LVDS signals are DDR, so the bit rate on some of those LVDS signals will be 250Mbps.

Will I get a "hail mary" pass by virtue of this being a receive-only interface, or should I bite the bullet, halt assembly of these prototypes and try to rework the 7 balls (buried inside the array of course) so they receive 2.5V?


it will most likely work just fine LVDS receivers are really just comparators, I've seen Xilinx say that it will work
with the exception if you use the buildin termination it might not be quite the right value

output is worse, on Zynq the LVDS output turn off when the bank voltage is above ~2.9V to protect the transistors, aprrently they can't have the same voltage as the ones for CMOS


 

Offline asmi

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On Xilinx's 7 series VCCIO doesn't matter if you want to use LVDS inputs and no onchip termination. So check the datasheet for your FPGA to see if it's the same. If you did plan to use onchip termination, you can opt not to and fit 100 Ohm 0402 or 0201 resistor (size depends on the pitch of your FPGA) under BGA across breakout vias. At 250 Mbps you should be OK.
If 2.5 V is a requirement for your FPGA, I wouldn't even bother assembling the board and would do a respin right away, as I doubt there is a good way you can rework VCCIO balls because generally they are connected directly to the power plane and there is likely no way to sever that connection.

Offline aandrewTopic starter

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Hey everyone. Just an update.

I have successfully used the 10MHz and 125MHz clocks coming in on some of these LVDS signals to drive the PLL and get basic blinky logic working. At least at first glance it looks like I may have succeeded despite the wrong I/O voltage on these banks with LVDS. Further testing will tell if I can hit 250Mbps on the DDR data, but for now it looks like I'm still hanging on. :-)
 


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