This is one of those dumb mistakes that made it through review.
Altera MAX10M08DAF, I have a number of LVDS inputs on banks 5 and 6. I connected the VCCIO for these banks to 3.3V and not 2.5V as is specified in the manual.
This is a BGA device and it's going to be a royal PITA to repair this, but I'm literally a day or two out from the parts being populated on the errored boards so if it needs to be fixed, this is the best time to do it.
My question is how bad of a screwup is this? The LVDS signals are all inputs to the FPGA, and the maximum clock frequency will be 125MHz, and some of those LVDS signals are DDR, so the bit rate on some of those LVDS signals will be 250Mbps.
Will I get a "hail mary" pass by virtue of this being a receive-only interface, or should I bite the bullet, halt assembly of these prototypes and try to rework the 7 balls (buried inside the array of course) so they receive 2.5V?