Whats the fastest way to count on an FPGA?

[frogmaster]

Hi,

I'm asking partially out of curiosity. I got triggered by some video showing how to typically implement a counter only with two JK-flip-flops and that got me thinking.

What is the most efficient, i.e. fast, way to 'simply' count up with an FPGA, maybe without a clock. Especially interesting would be solutions that are not really obvious ones and work due to the way CLBs are laid-out or something.

I've seen Gray Counters perform better than typical HDL implementations and also some weird Carry-Chain stuff.

Any ideas welcome.


Regards

[hamster_nz]

A lot depends on your application - what are you wanting to counting and why?

The quickest way to count 'something' is to combine various techniques. A very fast 'something' to prescale the input, followed by a longer (slower) counter to give you lots of digits. For example, you might use a high speed transceiver to capture the input 40 bits at a time, and then have logic behind that to count the number of 0-to-1 transitions.

The CLB logic must be quicker than the clocking network that supports it, so it is usually the clocking network's performance is the limiting factor - if it is something else like carry chain length then you are doing it wrong. This also hints that if you are only CLBs for your counter you should try to avoid using the logic's clocking networks at the very fast part of the counter - i.e. maybe route the input signal directly onto a flip-flop's CLK input, rather than through clock buffers.

[frogmaster]

Thanks for your reply!

A lot depends on your application - what are you wanting to counting and why?

Nothing specific, really. I'm thinking about measuring a signal (not necessarily a periodic one, but maybe) that's near 800MHz+ on lower end parts. Just trying to make sense of it. I've seen people building TDCs and so on, wondering whats possible in that regard.