You have to respect the limits
emm, "wait" had nothing to deal with "integers".
bad example!
The VHDL language contains the beautiful concept of the integer and intger subtype, which is basically an integer with constraints on its minimum and maximum values.
Thus you are defining a data-type which comes with borders, left and right.
So, why doesn't ISE use it? It's simply silly!
If you use integer inside a counter the code still fully benefits from the advantages of strong typing. Of course, a tool such as a synthesizer has no difficulty in working out the representation details for implementation. Therefore, things are exactly how we want them to be.
Integers ARE synthetizable!
If this were all that there was to it, we could claim that VHDL was superior to Verilog on this matter, and we could recommend the general usage of integer subtypes. Indeed, I believe that integer subtypes are underutilized and that they should be used whenever possible. Unfortunately, there is one major obstacle that prevents them from providing a general solution: VHDL integer type itself, which is the base type of integer subtypes, has impractically small constraints on its minimum and maximum values. Although the standard defines them as minimal constraints that an implementation might relax, for portability reasons they are hard constraints in practice. As a result, VHDL integers cannot represent bit widths beyond 32 bits.
That is the only problem you have with big numbers!
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I mean, there's
nothing wrong about using integers for RTL per se, but there are reasons that some avoid it. This really is a question about subjective "best practice".
Principally: I'm in favour of using constrained integers whenever possible. I sometimes do it, but in practice when writing for synthesis and I don't have to spend much time on simulating things (e.g. on Modelsim) then I immediately stick to signed and unsigned, just to avoid to deal with leakages in the language implementation because I find them a bit irritating.