Poll

Which HDL do You Use?

VHDL
38 (55.1%)
Verilog
23 (33.3%)
SystemVerilog
6 (8.7%)
Something Else
2 (2.9%)

Total Members Voted: 68

Author Topic: Which HDL do You Use?  (Read 11182 times)

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Offline Sal AmmoniacTopic starter

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Which HDL do You Use?
« on: August 14, 2017, 06:18:16 pm »
I'm curious as to how popular each of the two main HDL languages are among the people on this forum.
Complexity is the number-one enemy of high-quality code.
 

Offline legacy

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Re: Which HDL do You Use?
« Reply #1 on: August 14, 2017, 07:27:22 pm »
VHDL here
 

Offline legacy

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Re: Which HDL do You Use?
« Reply #2 on: August 14, 2017, 07:34:44 pm »
The right question is: why verilog?

I guess I have a theory: people probably find the type casting constraints in vhdl *limit* how fast they can work. In part it has to do with familiarity with the language.

ain't it?  :D
 

Offline jmelson

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Re: Which HDL do You Use?
« Reply #3 on: August 14, 2017, 07:42:38 pm »
I use VHDL.  Once I learned how to write type conversions, I prefer having to be explicit.  I can read Verilog, and have worked on some Verilog projects, but I have figured out how to do what I want in VHDL, and just stay in that domain.  I often write the top level in structural VHDL, rest in behavioral.

I do understand if you are synthesizing really complex numerical algorithms that Verilog has some major advantages, but that is not the stuff I do.

Jon
 

Offline legacy

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Re: Which HDL do You Use?
« Reply #4 on: August 14, 2017, 08:15:55 pm »
yup, vhdl has some limitations with "integers", they are 32bit, thus ... you need extra care if you use them for mathematical algorithms.


Is there a tool which converts vhdl into verilog?
 

Offline rstofer

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Re: Which HDL do You Use?
« Reply #5 on: August 14, 2017, 08:21:38 pm »
Strictly as a hobbyist, I started with VHDL about a dozen years ago.  I think I'm just too old to catch on to Verilog.  I have a couple of books, I should sit down and force myself to learn the language.

But what would I gain for the effort?

 

Offline kfnight

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Re: Which HDL do You Use?
« Reply #6 on: August 14, 2017, 08:56:35 pm »
SystemVerilog is the HDL for me, especially when I can use all its features. I also use it for design verification. I learned VHDL when getting my undergraduate degree, but when I look at it now it's too verbose for my tastes.
 

Offline Sal AmmoniacTopic starter

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Re: Which HDL do You Use?
« Reply #7 on: August 14, 2017, 09:03:41 pm »
The right question is: why verilog?

I've heard it said that VHDL is favored by Europeans and Verilog is favored by North Americans (except for those working in the defense industry, which favors VHDL).

I don't know if that's true, but I know there are exceptions (e.g. ARM uses Verilog). Perhaps Americans prefer the more C-like syntax of Verilog over the Ada-like syntax of VHDL.
Complexity is the number-one enemy of high-quality code.
 

Offline NorthGuy

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Re: Which HDL do You Use?
« Reply #8 on: August 14, 2017, 09:15:04 pm »
I use VHDL, but it is pure coincidence. If there was a reason to switch to Verilog, I wouldn't mind. But IMHO they're very similar.

If there was another, simpler language which would let me cut down on typing, I'd probably go with it.
 

Offline nanofrog

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Re: Which HDL do You Use?
« Reply #9 on: August 14, 2017, 09:26:29 pm »
VHDL here
Same.

I've heard it said that VHDL is favored by Europeans and Verilog is favored by North Americans (except for those working in the defense industry, which favors VHDL).

I don't know if that's true, but I know there are exceptions (e.g. ARM uses Verilog). Perhaps Americans prefer the more C-like syntax of Verilog over the Ada-like syntax of VHDL.
I've heard of your first statement as well, and like you, I don't know if it's true either.  :-//

For disclosure, I also learned it as an undergrad and worked in the defense industry. So you could say the deck was stacked in favor of VHDL in my case.  :P
 

Offline djacobow

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Re: Which HDL do You Use?
« Reply #10 on: August 14, 2017, 10:48:37 pm »
I learned VHDL as an undergrad, then my first job I used something called iHDL while at Intel, then after that nearly 100% Verilog.

I found VHDL to be verbose, but that didn't really make me too crazy. What did make me crazy was the incredibly slow compilation and utterly useless error messages, often pointing to errors hundreds of lines away from the source of the problem. Both of those are issues with the tool (MGC mid-1990s), not the language (to a degree), but they were deal killers for me. Switching to Verilog and later NC Verilog, and being able to trivially link real object code compiled from other languages (for integrating models you just don't want to do in a real hdl, or interactive with acceleration hardware) sort of sealed the deal. Also, Verilog simulations were just faster back then.

These days, of course, I'm sure VHDL has everything that Verilog has and works just as well.

One thing I liked about VHDL that Verilog at the time lacked were generate statements.
 

Offline zeqing

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Re: Which HDL do You Use?
« Reply #11 on: August 15, 2017, 08:31:45 am »
VHDL, 5 years before when i was in the colleague. ...
 

Offline legacy

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Re: Which HDL do You Use?
« Reply #12 on: August 15, 2017, 12:27:22 pm »
A few problem I have with VHDL is related to functions and procedures since I have written a tool able to extract interfaces (in C words you would say function-prototypes) from package-body (implementation).

"Package" and "Package-body" should be two independent units, like "C file" (where you put function-implementation and "H file" (where you put function-prototypes), the same applies to Modula2 and ADA, and VHDL derives from a language that should promote "modules", but ISE and Simulators don't accept information split in different files! Thus I can't put interfaces in a file and implementation in another file, I am obliged to put them into the same file  :palm:

It's a bit irritating.

 

Offline legacy

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Re: Which HDL do You Use?
« Reply #13 on: August 15, 2017, 12:38:51 pm »
Another irritating issue is related to integers. According to VHDL specification, the predefined attribute e.g. 'left can be applied to integer type, but apparently this isn't supported by some synthesis tools and simulators.

Modelsim accepts it, it says counter0'right is fine as well as counter0'left, but Xilinx ISE webpack claims that it's not supported when counter0 is defined as integer, it says it's OK if you define it as unsigned or std_vector_logic :palm: :palm: :palm:

Code: [Select]
  constant counter0_right    : integer := 15;       
  signal counter0            : integer range 0 to counter0_right:=0;   

...
    elsif rising_edge(in_clock) then     
        if (counter0 < counter0_right) then
          counter0   <= counter0 +1;
        else
...

They same applies to for-loop when you try to use 'range for the counter.

And again you have to work around it  :palm:

Which makes it irritating because you feel that the language implementation is not consistent.
 

Offline nctnico

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Re: Which HDL do You Use?
« Reply #14 on: August 15, 2017, 12:59:58 pm »
That is no surprise because an integer isn't really synthesizable. You should used signed and unsigned types for synthesizable logic.
There are small lies, big lies and then there is what is on the screen of your oscilloscope.
 

Offline legacy

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Re: Which HDL do You Use?
« Reply #15 on: August 15, 2017, 01:14:14 pm »
That is no surprise because an integer isn't really synthesizable. You should used signed and unsigned types for synthesizable logic.

I am talking about THE language, no matter if it's synthesizable or not, if you define a language to be consistent you MUST be able to have all the features for every types.

Here we have exceptions, like you can use certain features for a data-type (vectors) wheres the same features is not allowed for another data-type(integers): this is a mess!

Also, integers *ARE* synthesizable, they are converted into unsigned according to the proper bit-size, which is automatically set!

The difference between integers and unsigned is mainly inside the simulator, since integers trap bound-check and this makes you able to catch bugs.
 

Offline nctnico

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Re: Which HDL do You Use?
« Reply #16 on: August 15, 2017, 01:19:07 pm »
That is no surprise because an integer isn't really synthesizable. You should used signed and unsigned types for synthesizable logic.
I am talking about THE language, no matter if it's synthesizable or not, if you define a language to be consistent you MUST be able to have all the features for every types.
You have to respect the limits. For example wait() is also not synthesizable for FPGAs (at least not in the tools I know about).
Xilinx has a very thourough guide on what their synthesizer supports and how certain VHDL constructs translate to hardware.
There are small lies, big lies and then there is what is on the screen of your oscilloscope.
 

Offline legacy

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Re: Which HDL do You Use?
« Reply #17 on: August 15, 2017, 01:32:01 pm »
You have to respect the limits

emm, "wait" had nothing to deal with "integers".
bad example!

The VHDL language contains the beautiful concept of the integer and intger subtype, which is basically an integer with constraints on its minimum and maximum values.

Thus you are defining a data-type which comes with borders, left and right.
So, why doesn't ISE use it? It's simply silly!

If you use integer inside a counter the code still fully benefits from the advantages of strong typing. Of course, a tool such as a synthesizer has no difficulty in working out the representation details for implementation. Therefore, things are exactly how we want them to be.

Integers ARE synthetizable!

If this were all that there was to it, we could claim that VHDL was superior to Verilog on this matter, and we could recommend the general usage of integer subtypes. Indeed, I believe that integer subtypes are underutilized and that they should be used whenever possible. Unfortunately, there is one major obstacle that prevents them from providing a general solution: VHDL integer type itself, which is the base type of integer subtypes, has impractically small constraints on its minimum and maximum values. Although the standard defines them as minimal constraints that an implementation might relax, for portability reasons they are hard constraints in practice. As a result, VHDL integers cannot represent bit widths beyond 32 bits.

That is the only problem you have with big numbers!

------

I mean, there's nothing wrong about using integers for RTL per se, but there are reasons that some avoid it. This really is a question about subjective "best practice".

Principally: I'm in favour of using constrained integers whenever possible. I sometimes do it, but in practice when writing for synthesis and I don't have to spend much time on simulating things (e.g. on Modelsim) then I immediately stick to signed and unsigned, just to avoid to deal with leakages in the language implementation because I find them a bit irritating.
« Last Edit: August 15, 2017, 01:48:10 pm by legacy »
 

Offline ehughes

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Re: Which HDL do You Use?
« Reply #18 on: August 15, 2017, 01:45:42 pm »
Verilog & SystemVerilog.

The verification features in SystemVerilog are very nice as are the addition of interfaces.

VHDL is too verbose for my taste.   Way too much boiler plate.     People often quote its strict typing system to be a feature.       The reality is that if you are not writing self checking test benches for your code,   all of the VHDL semantics are a waste of time.

After all,  ARM does all of their designs in Verilog.   It is hard to argue with success.    I believe Apple, NVidia, Qualcomm, etc  use Verilog for design and verification.


https://homepages.thm.de/~hg53/hes-ws1617/aufgabe1/Cooley-VHDL-Verilog.html
 

Offline nctnico

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Re: Which HDL do You Use?
« Reply #19 on: August 15, 2017, 02:05:17 pm »
Verilog & SystemVerilog.

The verification features in SystemVerilog are very nice as are the addition of interfaces.

VHDL is too verbose for my taste.   Way too much boiler plate.     People often quote its strict typing system to be a feature.       The reality is that if you are not writing self checking test benches for your code,   all of the VHDL semantics are a waste of time.

After all,  ARM does all of their designs in Verilog.   It is hard to argue with success.    I believe Apple, NVidia, Qualcomm, etc  use Verilog for design and verification.
Monkey see - monkey do is hardly a valid argument. The problem is many people only use a very limited subset of VHDL. Like using MS Word to print pages with the alphabet and then use scissors to cut out the letters and glue to stick them on a piece of paper to make the wanted text.
There are small lies, big lies and then there is what is on the screen of your oscilloscope.
 

Offline ehughes

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Re: Which HDL do You Use?
« Reply #20 on: August 15, 2017, 02:16:01 pm »
Quote
Monkey see - monkey do is hardly a valid argument.

When the monkey ships products in the quantities of hundreds of millions and is in literally every device on the planet,  it is hard to make an argument for academic purity.



   





 

Offline nctnico

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Re: Which HDL do You Use?
« Reply #21 on: August 15, 2017, 02:23:46 pm »
Quote
Monkey see - monkey do is hardly a valid argument.
When the monkey ships products in the quantities of hundreds of millions and is in literally every device on the planet,  it is hard to make an argument for academic purity.
It still doesn't prove there is a better way today. VHDL support has improved a lot over the past decades. Perhaps Verilog was the best tool when the ARM core was invented decades ago (or the person who worked on it initially preferred Verilog) but today the people at ARM may have choosen differently.
There are small lies, big lies and then there is what is on the screen of your oscilloscope.
 

Offline legacy

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Re: Which HDL do You Use?
« Reply #22 on: August 15, 2017, 02:31:02 pm »
A lot of dudes use Verilog to describe their softcores.
Even at CERN. It's simple a fact. I don't know why.
 

Offline legacy

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Re: Which HDL do You Use?
« Reply #23 on: August 15, 2017, 03:34:59 pm »
monkey do is hardly a valid argument

like yours on integers, I suppose.
 

Offline Bruce Abbott

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Re: Which HDL do You Use?
« Reply #24 on: August 15, 2017, 03:46:59 pm »
Another irritating issue is related to integers. According to VHDL specification, the predefined attribute e.g. 'left can be applied to integer type, but apparently this isn't supported by some synthesis tools and simulators.

Modelsim accepts it, it says counter0'right is fine as well as counter0'left, but Xilinx ISE webpack claims that it's not supported when counter0 is defined as integer, it says it's OK if you define it as unsigned or std_vector_logic :palm: :palm: :palm:
Why would an integer have attributes 'left' and 'right'? Doesn't make sense. What would you use them for?
 


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