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Electronics => Microcontrollers => Topic started by: Sal Ammoniac on August 14, 2017, 06:18:16 pm

Title: Which HDL do You Use?
Post by: Sal Ammoniac on August 14, 2017, 06:18:16 pm
I'm curious as to how popular each of the two main HDL languages are among the people on this forum.
Title: Re: Which HDL do You Use?
Post by: legacy on August 14, 2017, 07:27:22 pm
VHDL here
Title: Re: Which HDL do You Use?
Post by: legacy on August 14, 2017, 07:34:44 pm
The right question is: why verilog?

I guess I have a theory: people probably find the type casting constraints in vhdl *limit* how fast they can work. In part it has to do with familiarity with the language.

ain't it?  :D
Title: Re: Which HDL do You Use?
Post by: jmelson on August 14, 2017, 07:42:38 pm
I use VHDL.  Once I learned how to write type conversions, I prefer having to be explicit.  I can read Verilog, and have worked on some Verilog projects, but I have figured out how to do what I want in VHDL, and just stay in that domain.  I often write the top level in structural VHDL, rest in behavioral.

I do understand if you are synthesizing really complex numerical algorithms that Verilog has some major advantages, but that is not the stuff I do.

Jon
Title: Re: Which HDL do You Use?
Post by: legacy on August 14, 2017, 08:15:55 pm
yup, vhdl has some limitations with "integers", they are 32bit, thus ... you need extra care if you use them for mathematical algorithms.


Is there a tool which converts vhdl into verilog?
Title: Re: Which HDL do You Use?
Post by: rstofer on August 14, 2017, 08:21:38 pm
Strictly as a hobbyist, I started with VHDL about a dozen years ago.  I think I'm just too old to catch on to Verilog.  I have a couple of books, I should sit down and force myself to learn the language.

But what would I gain for the effort?

Title: Re: Which HDL do You Use?
Post by: kfnight on August 14, 2017, 08:56:35 pm
SystemVerilog is the HDL for me, especially when I can use all its features. I also use it for design verification. I learned VHDL when getting my undergraduate degree, but when I look at it now it's too verbose for my tastes.
Title: Re: Which HDL do You Use?
Post by: Sal Ammoniac on August 14, 2017, 09:03:41 pm
The right question is: why verilog?

I've heard it said that VHDL is favored by Europeans and Verilog is favored by North Americans (except for those working in the defense industry, which favors VHDL).

I don't know if that's true, but I know there are exceptions (e.g. ARM uses Verilog). Perhaps Americans prefer the more C-like syntax of Verilog over the Ada-like syntax of VHDL.
Title: Re: Which HDL do You Use?
Post by: NorthGuy on August 14, 2017, 09:15:04 pm
I use VHDL, but it is pure coincidence. If there was a reason to switch to Verilog, I wouldn't mind. But IMHO they're very similar.

If there was another, simpler language which would let me cut down on typing, I'd probably go with it.
Title: Re: Which HDL do You Use?
Post by: nanofrog on August 14, 2017, 09:26:29 pm
VHDL here
Same.

I've heard it said that VHDL is favored by Europeans and Verilog is favored by North Americans (except for those working in the defense industry, which favors VHDL).

I don't know if that's true, but I know there are exceptions (e.g. ARM uses Verilog). Perhaps Americans prefer the more C-like syntax of Verilog over the Ada-like syntax of VHDL.
I've heard of your first statement as well, and like you, I don't know if it's true either.  :-//

For disclosure, I also learned it as an undergrad and worked in the defense industry. So you could say the deck was stacked in favor of VHDL in my case.  :P
Title: Re: Which HDL do You Use?
Post by: djacobow on August 14, 2017, 10:48:37 pm
I learned VHDL as an undergrad, then my first job I used something called iHDL while at Intel, then after that nearly 100% Verilog.

I found VHDL to be verbose, but that didn't really make me too crazy. What did make me crazy was the incredibly slow compilation and utterly useless error messages, often pointing to errors hundreds of lines away from the source of the problem. Both of those are issues with the tool (MGC mid-1990s), not the language (to a degree), but they were deal killers for me. Switching to Verilog and later NC Verilog, and being able to trivially link real object code compiled from other languages (for integrating models you just don't want to do in a real hdl, or interactive with acceleration hardware) sort of sealed the deal. Also, Verilog simulations were just faster back then.

These days, of course, I'm sure VHDL has everything that Verilog has and works just as well.

One thing I liked about VHDL that Verilog at the time lacked were generate statements.
Title: Re: Which HDL do You Use?
Post by: zeqing on August 15, 2017, 08:31:45 am
VHDL, 5 years before when i was in the colleague. ...
Title: Re: Which HDL do You Use?
Post by: legacy on August 15, 2017, 12:27:22 pm
A few problem I have with VHDL is related to functions and procedures since I have written a tool able to extract interfaces (in C words you would say function-prototypes) from package-body (implementation).

"Package" and "Package-body" should be two independent units, like "C file" (where you put function-implementation and "H file" (where you put function-prototypes), the same applies to Modula2 and ADA, and VHDL derives from a language that should promote "modules", but ISE and Simulators don't accept information split in different files! Thus I can't put interfaces in a file and implementation in another file, I am obliged to put them into the same file  :palm:

It's a bit irritating.

Title: Re: Which HDL do You Use?
Post by: legacy on August 15, 2017, 12:38:51 pm
Another irritating issue is related to integers. According to VHDL specification, the predefined attribute e.g. 'left can be applied to integer type, but apparently this isn't supported by some synthesis tools and simulators.

Modelsim accepts it, it says counter0'right is fine as well as counter0'left, but Xilinx ISE webpack claims that it's not supported when counter0 is defined as integer, it says it's OK if you define it as unsigned or std_vector_logic :palm: :palm: :palm:

Code: [Select]
  constant counter0_right    : integer := 15;       
  signal counter0            : integer range 0 to counter0_right:=0;   

...
    elsif rising_edge(in_clock) then     
        if (counter0 < counter0_right) then
          counter0   <= counter0 +1;
        else
...

They same applies to for-loop when you try to use 'range for the counter.

And again you have to work around it  :palm:

Which makes it irritating because you feel that the language implementation is not consistent.
Title: Re: Which HDL do You Use?
Post by: nctnico on August 15, 2017, 12:59:58 pm
That is no surprise because an integer isn't really synthesizable. You should used signed and unsigned types for synthesizable logic.
Title: Re: Which HDL do You Use?
Post by: legacy on August 15, 2017, 01:14:14 pm
That is no surprise because an integer isn't really synthesizable. You should used signed and unsigned types for synthesizable logic.

I am talking about THE language, no matter if it's synthesizable or not, if you define a language to be consistent you MUST be able to have all the features for every types.

Here we have exceptions, like you can use certain features for a data-type (vectors) wheres the same features is not allowed for another data-type(integers): this is a mess!

Also, integers *ARE* synthesizable, they are converted into unsigned according to the proper bit-size, which is automatically set!

The difference between integers and unsigned is mainly inside the simulator, since integers trap bound-check and this makes you able to catch bugs.
Title: Re: Which HDL do You Use?
Post by: nctnico on August 15, 2017, 01:19:07 pm
That is no surprise because an integer isn't really synthesizable. You should used signed and unsigned types for synthesizable logic.
I am talking about THE language, no matter if it's synthesizable or not, if you define a language to be consistent you MUST be able to have all the features for every types.
You have to respect the limits. For example wait() is also not synthesizable for FPGAs (at least not in the tools I know about).
Xilinx has a very thourough guide on what their synthesizer supports and how certain VHDL constructs translate to hardware.
Title: Re: Which HDL do You Use?
Post by: legacy on August 15, 2017, 01:32:01 pm
You have to respect the limits

emm, "wait" had nothing to deal with "integers".
bad example!

The VHDL language contains the beautiful concept of the integer and intger subtype, which is basically an integer with constraints on its minimum and maximum values.

Thus you are defining a data-type which comes with borders, left and right.
So, why doesn't ISE use it? It's simply silly!

If you use integer inside a counter the code still fully benefits from the advantages of strong typing. Of course, a tool such as a synthesizer has no difficulty in working out the representation details for implementation. Therefore, things are exactly how we want them to be.

Integers ARE synthetizable!

If this were all that there was to it, we could claim that VHDL was superior to Verilog on this matter, and we could recommend the general usage of integer subtypes. Indeed, I believe that integer subtypes are underutilized and that they should be used whenever possible. Unfortunately, there is one major obstacle that prevents them from providing a general solution: VHDL integer type itself, which is the base type of integer subtypes, has impractically small constraints on its minimum and maximum values. Although the standard defines them as minimal constraints that an implementation might relax, for portability reasons they are hard constraints in practice. As a result, VHDL integers cannot represent bit widths beyond 32 bits.

That is the only problem you have with big numbers!

------

I mean, there's nothing wrong about using integers for RTL per se, but there are reasons that some avoid it. This really is a question about subjective "best practice".

Principally: I'm in favour of using constrained integers whenever possible. I sometimes do it, but in practice when writing for synthesis and I don't have to spend much time on simulating things (e.g. on Modelsim) then I immediately stick to signed and unsigned, just to avoid to deal with leakages in the language implementation because I find them a bit irritating.
Title: Re: Which HDL do You Use?
Post by: ehughes on August 15, 2017, 01:45:42 pm
Verilog & SystemVerilog.

The verification features in SystemVerilog are very nice as are the addition of interfaces.

VHDL is too verbose for my taste.   Way too much boiler plate.     People often quote its strict typing system to be a feature.       The reality is that if you are not writing self checking test benches for your code,   all of the VHDL semantics are a waste of time.

After all,  ARM does all of their designs in Verilog.   It is hard to argue with success.    I believe Apple, NVidia, Qualcomm, etc  use Verilog for design and verification.


https://homepages.thm.de/~hg53/hes-ws1617/aufgabe1/Cooley-VHDL-Verilog.html
Title: Re: Which HDL do You Use?
Post by: nctnico on August 15, 2017, 02:05:17 pm
Verilog & SystemVerilog.

The verification features in SystemVerilog are very nice as are the addition of interfaces.

VHDL is too verbose for my taste.   Way too much boiler plate.     People often quote its strict typing system to be a feature.       The reality is that if you are not writing self checking test benches for your code,   all of the VHDL semantics are a waste of time.

After all,  ARM does all of their designs in Verilog.   It is hard to argue with success.    I believe Apple, NVidia, Qualcomm, etc  use Verilog for design and verification.
Monkey see - monkey do is hardly a valid argument. The problem is many people only use a very limited subset of VHDL. Like using MS Word to print pages with the alphabet and then use scissors to cut out the letters and glue to stick them on a piece of paper to make the wanted text.
Title: Re: Which HDL do You Use?
Post by: ehughes on August 15, 2017, 02:16:01 pm
Quote
Monkey see - monkey do is hardly a valid argument.

When the monkey ships products in the quantities of hundreds of millions and is in literally every device on the planet,  it is hard to make an argument for academic purity.



   





Title: Re: Which HDL do You Use?
Post by: nctnico on August 15, 2017, 02:23:46 pm
Quote
Monkey see - monkey do is hardly a valid argument.
When the monkey ships products in the quantities of hundreds of millions and is in literally every device on the planet,  it is hard to make an argument for academic purity.
It still doesn't prove there is a better way today. VHDL support has improved a lot over the past decades. Perhaps Verilog was the best tool when the ARM core was invented decades ago (or the person who worked on it initially preferred Verilog) but today the people at ARM may have choosen differently.
Title: Re: Which HDL do You Use?
Post by: legacy on August 15, 2017, 02:31:02 pm
A lot of dudes use Verilog to describe their softcores.
Even at CERN. It's simple a fact. I don't know why.
Title: Re: Which HDL do You Use?
Post by: legacy on August 15, 2017, 03:34:59 pm
monkey do is hardly a valid argument

like yours on integers, I suppose.
Title: Re: Which HDL do You Use?
Post by: Bruce Abbott on August 15, 2017, 03:46:59 pm
Another irritating issue is related to integers. According to VHDL specification, the predefined attribute e.g. 'left can be applied to integer type, but apparently this isn't supported by some synthesis tools and simulators.

Modelsim accepts it, it says counter0'right is fine as well as counter0'left, but Xilinx ISE webpack claims that it's not supported when counter0 is defined as integer, it says it's OK if you define it as unsigned or std_vector_logic :palm: :palm: :palm:
Why would an integer (https://en.wikipedia.org/wiki/Integer) have attributes 'left' and 'right'? Doesn't make sense. What would you use them for?
Title: Re: Which HDL do You Use?
Post by: nctnico on August 15, 2017, 03:48:29 pm
monkey do is hardly a valid argument
like yours on integers, I suppose.
Just read about the pros and cons and you'll see using the signed and unsigned types is much better if you want the synthesize your VHDL code. Banging your head agains't the wall won't make it move but you will get a headache.
Title: Re: Which HDL do You Use?
Post by: legacy on August 15, 2017, 03:57:12 pm
Just read about the pros and cons and you'll see using the signed and unsigned types is much better if you want the synthesize your VHDL code. Banging your head agains't the wall won't make it move but you will get a headache.

 :blah: :blah: :blah: :blah:

Dude, all bullshit until you give precise points.
Title: Re: Which HDL do You Use?
Post by: ehughes on August 15, 2017, 04:14:11 pm
Quote
It still doesn't prove there is a better way today.

It's called SystemVerilog.      You get much better verification tools,  simpler synthesis constructs to convey intent and better support for specification of complex interfaces.     

That and my other objection to VHDL is that it was created by the US DoD.  The king of most inefficient systems engineering on the planet.  Combine the DoD with Academia and you end up with a monstrosity.

Can it do some cool things?  Yea.    Is it the most practical way to solve a problem.  No.


Title: Re: Which HDL do You Use?
Post by: nctnico on August 15, 2017, 04:19:08 pm
Just read about the pros and cons and you'll see using the signed and unsigned types is much better if you want the synthesize your VHDL code. Banging your head agains't the wall won't make it move but you will get a headache.

 :blah: :blah: :blah: :blah:

Dude, all bullshit until you give precise points.
Why should *I* provide precise points if you clearly have a working internet connection and access to Google? Just take the pointers and do the research yourself.
Title: Re: Which HDL do You Use?
Post by: Sal Ammoniac on August 15, 2017, 04:52:20 pm
It's called SystemVerilog.      You get much better verification tools,  simpler synthesis constructs to convey intent and better support for specification of complex interfaces.

How mature is SystemVerilog support in Vivado 2017.2? Is it mature enough for production use?
Title: Re: Which HDL do You Use?
Post by: ehughes on August 16, 2017, 05:45:20 pm
Quote
How mature is SystemVerilog support in Vivado 2017.2? Is it mature enough for production use?


Yes.
Title: Re: Which HDL do You Use?
Post by: legacy on August 16, 2017, 07:09:38 pm
Nice :D

which tool-set do you use for it?
(simulator, compiler, analyzer, editor, etc)
Title: Re: Which HDL do You Use?
Post by: obiwanjacobi on August 17, 2017, 09:56:35 am
As a beginner hobbyist learned VHDL, but I found it frustratingly verbose. Thinking of how I would design a hardware language, SystemVerilog came closest and so I am trying to switch to that (on my next project).

As with any hardware language, the learning curve is considerable.
Title: Re: Which HDL do You Use?
Post by: chris_leyson on August 17, 2017, 10:30:15 am
VHDL here, only because I couldn't get my head around Verilog syntax, I guess it wouldn't hurt to make the effort to learn Verilog.
Title: Re: Which HDL do You Use?
Post by: legacy on August 17, 2017, 10:32:02 am
and 'right'? Doesn't make sense. What would you use them for?

in first place the language MUST be consistent.
integers is a datatype, thus it MUST have the same property of other data-types.

in second place, upper and lower borders are useful when you give them a sub-range
it's very very useful when you describe something that aims to be generic

e.g. you have a counter under the sub-range of {min .. max}, and you want to write a loop.
If borders of integers are not supported by some tool (VHDL as language has it, ModelSim does support it, ISE doesn't), then you end with something that needs to have an explicit constant declared somewhere in the code

and this is more error-prone.
Title: Re: Which HDL do You Use?
Post by: legacy on August 17, 2017, 11:21:25 am
Code: [Select]
for i in in_data'range loop

if in_data is described as unsigned or std_logic_vector, then ISE accepts the 'range operator!
look at the code, how beautiful it goes!

you might want to do the same with integers to describe a counter!
Title: Re: Which HDL do You Use?
Post by: legacy on August 17, 2017, 11:55:13 am
It seems that Verilog is more used in ASIC than VHDL in the same business area thanks to its property of being able to offer functional coverage with less effort

interesting  :D
Title: Re: Which HDL do You Use?
Post by: Cerebus on August 17, 2017, 01:03:47 pm
It seems that Verilog is more used in ASIC than VHDL in the same business area thanks to its property of being able to offer functional coverage with less effort

interesting  :D

I suspect that the relative popularity of Verilog in ASIC design is more down to the fact that Verilog has always had better support for timing than VHDL, so much so that in the first iterations of both languages Verilog had fully formed back annotation of timing, VHDL had none, nada, zip. Then consider how ASIC designers like to do little timing tricks (series of buffers as delay lines, combinatorial feedback etc.) and it becomes clear that VHDL would have, at first, been virtually unusable for ASIC simulation and sign-off.
Title: Re: Which HDL do You Use?
Post by: legacy on August 17, 2017, 08:13:27 pm
Code: [Select]
for i in in_data'range loop

About the above property

Code: [Select]
  constant tick              : integer := (clock_frequency/debounce_frequency);
  signal   tick_counter      : integer range 0 to tick;

I am working on it just right now, here it is an example of what I find useful for me
Title: Re: Which HDL do You Use?
Post by: NorthGuy on August 18, 2017, 12:53:41 am
It would be interesting to know what the two people who voted "Something Else" are using.
Title: Re: Which HDL do You Use?
Post by: hamster_nz on August 18, 2017, 04:40:34 am
Code: [Select]
  constant tick              : integer := (clock_frequency/debounce_frequency);
  signal   tick_counter      : integer range 0 to tick;

I am working on it just right now, here it is an example of what I find useful for me

One thing I have yet to experiment with is the utility of this...

With using integer:

- Does it help during simulation/verification? 

- Does it ensure that tick_counter stays within range. (not sure, but I guess it should at least warn you during simulation)

- Does it enforce that it stays within the allowed range? e.g. if tick was 100, would the counter count 99, 100, 0 if the code was increment it?

- What is the point of an tick being integer if it doesn't go negative? Will it still have a sign bit? If you accidentally subtract 1 from 0, will it be -1?

- If you were worried about undefined reset states, or SEUs doesn't it hide too much to know the possible states?

- Aren't you relying on the smarts of the tools deduce the allowable range, dropping bits as needed:

I guess what I am asking is... do you still need to code something like:

Code: [Select]
  if tick_counter >= tick_counter'high then
   tick_counter <= 0;
  else
    tick_counter <= tick_counter+1;
  end if;

or can you code it like this:
Code: [Select]
    tick_counter <= tick_counter+1;  -- wraps at tick_counter'high

What (if anything) is wrong with:

Code: [Select]
  constant tick_counter_max : unsigned(31 downto 0) := unsigned(clock_frequency/debounce_frequency-1,32);
  signal   tick_counter          : unsigned(31 downto 0) := (others => '0')

  ...
  if tick_counter >= tick_counter_max then
   tick_counter <= 0;
  else
    tick_counter <= tick_counter+1;
  end if;
  ...


PS. Shouldn't it be:

Code: [Select]
  signal   tick_counter      : integer range 0 to tick-1;

(not that it really matters)
Title: Re: Which HDL do You Use?
Post by: hamster_nz on August 18, 2017, 06:30:46 am
One thing I have yet to experiment with is the utility of this...

With using integer:

- Does it help during simulation/verification? 

- Does it ensure that tick_counter stays within range. (not sure, but I guess it should at least warn you during simulation)

- Does it enforce that it stays within the allowed range? e.g. if tick was 100, would the counter count 99, 100, 0 if the code was increment it?

- What is the point of an tick being integer if it doesn't go negative? Will it still have a sign bit? If you accidentally subtract 1 from 0, will it be -1?

- If you were worried about undefined reset states, or SEUs doesn't it hide too much to know the possible states?

- Aren't you relying on the smarts of the tools deduce the allowable range, dropping bits as needed:

I guess what I am asking is... do you still need to code something like:

Code: [Select]
  if tick_counter >= tick_counter'high then
   tick_counter <= 0;
  else
    tick_counter <= tick_counter+1;
  end if;

or can you code it like this:
Code: [Select]
    tick_counter <= tick_counter+1;  -- wraps at tick_counter'high

So I fired up Vivado, and got an integer counter with range 0 to 100 and incremented it. after 3ms it was 299,998... with no warnings... humm.. where is the utility in that????  :-//
Title: Re: Which HDL do You Use?
Post by: legacy on August 18, 2017, 08:46:37 am
- Does it help during simulation/verification? 

yes

- Does it ensure that tick_counter stays within range. (not sure, but I guess it should at least warn you during simulation)

With ModelSim you always get "bond error" (severity level -> simulation halted) if an integers/positive/natural goes out of the range.

Quote
- What is the point of an tick being integer if it doesn't go negative? Will it still have a sign bit? If you accidentally subtract 1 from 0, will it be -1?

Do you prefer "natural" or "positive" ? Of course, if you can use it: integers is signed, and it's 32 bit range. Positive is unsigned 32bit. If someone needs a huge counter, he/she had better use a sub range of positive.

Quote
- If you were worried about undefined reset states, or SEUs doesn't it hide too much to know the possible states?

No because
- everything (even integers) is pre-initialized once declared, signal blablabla := INIT_VALUE;
- counters are integers, everything else is handled with "std_logic_vector" and "unsignend"
- they both propagate X and U status, and you can see and react to mistakes from the simulator

Nothing is hidden, the there is always a starting value for counters! It's the fist thing I check when I simulate.

Quote
Aren't you relying on the smarts of the tools deduce the allowable range, dropping bits as needed:

well, I wrote a simple VHDL parser as "analyzer", and it was relatively easy to read a integer signal, look at its range, and deduce how many bits it takes

x=get_abs_max(range_min, range_max) ==> n_bit=get_log2(x);

ModelSim is even smarter than my simple tool by several and several orders of magnitude, and so it's ISE.


my code looks like this, anyway

Code: [Select]
    if rising_edge(in_clock) then
      if state = idle then       
      else
        if tick_counter=tick then
          tick_counter<=0;
        else
          tick_counter <= tick_counter+1;
        end if;
      end if;

Code: [Select]
constant tick            : integer := clk_freq/baudrate;
signal   tick_counter    : integer range 0 to tick;   

[..]

        if tick_counter=tick then

It's a reload-to-zero trick, there is no 'high because ISE is not able to understand it, thus this solution works for both ModelSim and ISE.

In my experience, it's better using a "compare_equal" rather than "compare_less_than"
Title: Re: Which HDL do You Use?
Post by: legacy on August 18, 2017, 08:54:47 am
where is the utility in that????  :-//

Code: [Select]
error: bound check failed (#2), simulation failed

Next line of the log-console says which line of which file of code got the bound-checked failed.
So, you know where you have to look at.
Title: Re: Which HDL do You Use?
Post by: hamster_nz on August 18, 2017, 09:32:07 am
Ah! Found it!

For Vivado the default for Tools/Settings/Simuation xsim.elaborate.rangecheck is off. With it on it now it stops the sim when it should. That at least makes it useful for that.

In my experience, it's better using a "compare_equal" rather than "compare_less_than"

I tend to use >= in counters posted to the web, after being bitten a few times...

Code: [Select]
    if count = limit then
       count <= 0
    else
       count <= count + 1;
    end if;

Imagine the case when count is 20 bits (0 to ~1 million) as is 'limit', and limit dynamically changes - e.g. it is an input parameter to the module.

If 'limit' goes from 99 to 999 all is fine. If 'limit' changes from 999 to 99 then you have a 90% chance of the counter counting up all the way up to 2^20-1 before it cycles back to 0.

I'm happy to use that as a generic pattern, swapping a handful of LUTs for one less bug to hunt down after requirements change, making a 'constant' now not-so-constant....
Title: Re: Which HDL do You Use?
Post by: legacy on August 18, 2017, 10:34:13 am
(https://s17.postimg.org/5mc5fsa8f/Arise-v2-keyboard-timing.png)

Yup, for dynamic parameters your trick is better; here I am on a static parameters, I am designing the keyboard controller, counters are used to scan the matrix, perform debounces, transmit character (uart like).

All static parameters for counters  :D


edit:
p.s.
what about YOU, guys on Verilog?
Title: Re: Which HDL do You Use?
Post by: legacy on August 18, 2017, 03:05:45 pm
another annoying thing in VHDL is that case's choices must be a locally static expression, you can't define a constant and use it  :palm: :palm: :palm:

Code: [Select]
      case matrix_in1 is
        when event_none  => datakey2 <= get_datakey(0);
        when event_key01 => datakey2 <= get_datakey(1);

not good

Code: [Select]
      case matrix_in1 is
        when b"00000000000000000" => datakey2 <= get_datakey(0);
        when b"00000000000000001" => datakey2 <= get_datakey(1);

good
Title: Re: Which HDL do You Use?
Post by: nctnico on August 18, 2017, 04:05:05 pm
another annoying thing in VHDL is that case's choices must be a locally static expression, you can't define a constant and use it  :palm: :palm: :palm:

Code: [Select]
      case matrix_in1 is
        when event_none  => datakey2 <= get_datakey(0);
        when event_key01 => datakey2 <= get_datakey(1);

not good

Code: [Select]
      case matrix_in1 is
        when b"00000000000000000" => datakey2 <= get_datakey(0);
        when b"00000000000000001" => datakey2 <= get_datakey(1);

good
Ofcourse you can. Google VHDL enumerations: http://insights.sigasi.com/tech/vhdl-case-statements-can-do-without-others.html (http://insights.sigasi.com/tech/vhdl-case-statements-can-do-without-others.html)
An advantage of using an enumeration is that the synthesizer can select between one-hot or binary encoding. One-hot encoding makes for simpler logic.
Title: Re: Which HDL do You Use?
Post by: legacy on August 18, 2017, 04:55:33 pm
Ofcourse you can

I am not talking about
Code: [Select]
type state_t is (s1, s2, s3);
signal state: case_t;
case state
  when s1 =>

I am talking about
Code: [Select]
constant event_key01 := get_matrix_in(1);

case matrix_in
  when event_key =>

VHDL doesn't allow this!

Title: Re: Which HDL do You Use?
Post by: legacy on August 18, 2017, 05:00:10 pm
in VHDL (and this is a big mistake) enumeration is NOT equal to constant

thus VHDL claims that case choices MUST be a locally static expression

enumeration is static expression, thus accepted
BUT! formally even a constant is a static expression

The conclusion is:
VHDL, as language, is NOT consistent  :palm:
Title: Re: Which HDL do You Use?
Post by: nctnico on August 18, 2017, 05:02:17 pm
But what error do you get? At first sight it seems like some sort of type-clash to me.
From this page:
http://vhdl.renerta.com/mobile/source/vhd00014.htm (http://vhdl.renerta.com/mobile/source/vhd00014.htm)
Code: [Select]
P5:process
variable Code_of_Operation : INTEGER range 0 to 2;
constant Variable_1 : INTEGER := 0;
begin
  C6: case Code_of_Operation is
      when Variable_1 | Variable_1 + 1 =>
      Operation := 0;
      when Variable_1 + 2 =>
      Operation := 1;
  end case C6;
end process;
Title: Re: Which HDL do You Use?
Post by: legacy on August 18, 2017, 05:14:05 pm
ISE, ModelSim and ghdl: they all give the same error, and they don't accept constant as Case choice.
The example above smells "VHDL language improvement", new features may be :-//
Title: Re: Which HDL do You Use?
Post by: nctnico on August 18, 2017, 05:36:26 pm
I guess you already played with the VHDL 'version' settings  8)
Title: Re: Which HDL do You Use?
Post by: Sal Ammoniac on September 13, 2017, 01:19:38 am
One-hot encoding makes for simpler logic.

Is that always the case? The following article seems to imply that onehot encoding in FSMs leads to more complex logic.

http://www.sunburst-design.com/papers/CummingsSNUG2003SJ_SystemVerilogFSM.pdf (http://www.sunburst-design.com/papers/CummingsSNUG2003SJ_SystemVerilogFSM.pdf)
Title: Re: Which HDL do You Use?
Post by: Cerebus on September 13, 2017, 02:11:51 am
One-hot encoding makes for simpler logic.

Is that always the case? The following article seems to imply that onehot encoding in FSMs leads to more complex logic.

http://www.sunburst-design.com/papers/CummingsSNUG2003SJ_SystemVerilogFSM.pdf (http://www.sunburst-design.com/papers/CummingsSNUG2003SJ_SystemVerilogFSM.pdf)

Sometimes it will make for simpler logic, other times it'll make it worse.

An example of the "make it worse" case is something I wrote a few days ago. It's just a generator for half a dozen clocks that have to have a particular relationship to one another in time. The whole thing has 32 states. One clock is high for two of those, another two for 7 clocks each and so on. If you implement it as a counter and ROM, it's a doddle. If you implement it as 32 one hot states, it's a great big mess of OR gates, some 2 wide, some 7 and so on.
Title: Re: Which HDL do You Use?
Post by: Bassman59 on September 14, 2017, 12:12:09 am
That is no surprise because an integer isn't really synthesizable. You should used signed and unsigned types for synthesizable logic.

I use naturals and integers all the time in synthesizable code. The trick is to specify a range for the integer, which does two things. One, in simulation, you get an error if you ever try to assign a number outside the range, you get an error.

Two, the synthesizer is smart enough to know to limit the number of flip-flops created for the signal. So if you have a signal declared as:

Code: [Select]
signal foo : natural range 0 to 100;
the synthesizer will infer a 7-bit register.

Counting and doing math with std_logic_vectors is to be avoided.
Title: Re: Which HDL do You Use?
Post by: rstofer on September 14, 2017, 12:52:53 am
Counting and doing math with std_logic_vectors is to be avoided.

Why is that?  I realize it takes the inclusion of a non-standard library but it sure saves a lot of casting.

Most of the tutorials I have seen use SLVs for everything.  I know I'm supposed to change and I'm trying but I really don't know why it matters.  In the end, everything is an SLV.

If the answer revolves around simulation, it's just an exercise because I don't use the simulator.  Simple projects and other ways to debug.
Title: Re: Which HDL do You Use?
Post by: Bassman59 on September 14, 2017, 03:49:56 am
Counting and doing math with std_logic_vectors is to be avoided.

Why is that?  I realize it takes the inclusion of a non-standard library but it sure saves a lot of casting.

Why? Because we are humans and we do math with numbers, not with vectors of bits. Many times there is no need to do the casts, anyway. Counters, memory addresses, all sorts of things can remain ranged integers and never be converted to a bit-vector representation.

And yes, you can use naturals and integers on entity ports. (The exception, of course, is at the top level of your FPGA design.)

Quote
Most of the tutorials I have seen use SLVs for everything.  I know I'm supposed to change and I'm trying but I really don't know why it matters.  In the end, everything is an SLV.

The tutorials were written in the dark ages before synthesizers could deal with integers, and they've never been updated. Hell, some of them still write

Code: [Select]
if clk'event and clk = '1' then
Instead of

Code: [Select]
if rising_edge(clk) then
It would be nice if tutorials reflected the nice changes in the language since VHDL'93 ...

Quote
If the answer revolves around simulation, it's just an exercise because I don't use the simulator.  Simple projects and other ways to debug.

My projects are too complex to go without simulation.

You are free to code however you wish to code. But don't overlook the language's advantages.
Title: Re: Which HDL do You Use?
Post by: legacy on September 18, 2017, 01:42:10 pm
Code: [Select]
if clk'event and clk = '1' then

even the Xilinx "ISE v10.1/State CAD" (a tool included with ISE) uses this obsolete form :palm: :palm: :palm:
Title: Re: Which HDL do You Use?
Post by: nctnico on September 18, 2017, 03:56:42 pm
Counting and doing math with std_logic_vectors is to be avoided.
Why is that?  I realize it takes the inclusion of a non-standard library but it sure saves a lot of casting.

Most of the tutorials I have seen use SLVs for everything.
AFAIK the numerical library was added to VHDL 'later' and so using std_logic_vector stuck with many people. But nowadays you should use numeric types because it makes a lot of things easier (like doing calculations) or use a signal as an index for an array.
Title: Re: Which HDL do You Use?
Post by: Bassman59 on September 22, 2017, 08:56:13 pm
Code: [Select]
if clk'event and clk = '1' then

even the Xilinx "ISE v10.1/State CAD" (a tool included with ISE) uses this obsolete form :palm: :palm: :palm:

The language templates included with ISE 14.7 (the last version of ISE, from 2013) still use the obsolete idiom. The latest XST synthesis and style guide does use rising_edge(clk), though, as does the Vivado synthesis guide. Of course, they don't use the nice decorations, like labels for processes and such.
Title: Re: Which HDL do You Use?
Post by: Bassman59 on September 22, 2017, 09:15:01 pm
Counting and doing math with std_logic_vectors is to be avoided.
Why is that?  I realize it takes the inclusion of a non-standard library but it sure saves a lot of casting.

Most of the tutorials I have seen use SLVs for everything.
AFAIK the numerical library was added to VHDL 'later' and so using std_logic_vector stuck with many people. But nowadays you should use numeric types because it makes a lot of things easier (like doing calculations) or use a signal as an index for an array.

The original versions of VHDL did not allow for math operations on std_logic_vector types. You could do math on integernatural and real signals, but they weren't synthesizable (remember, this was 30 years ago!). Since most modeling was done using std_logic and its vector form std_logic_vector, Synopsys created a package, std_logic_arith, to define math operations on SLVs. A problem arises, which is how to handle unsigned and signed math, and the operators and functions were defined in packages std_logic_signed and std_logic_unsigned.

Synopsys decided that those decidedly non-standard libraries should be included in the ieee library, which is why you see it used as

use ieee.std_logic_arith.all;

instead of

use synopsys.std_logic_arith.all;

and it became the defacto standard.

A glaring problem emerges: what if you need to do unsigned and signed math in the same entity? What happens when you do:

use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
use ieee.std_logic_signed.all;


and then you want to do some math:

signal foo : std_logic_vector(7 downto 0);
signal bar : std_logic_vector(7 downto 0);
signal bletch : std_logic_vector(7 downto 0);

bletch <= foo + bar;


Is that operation signed or unsigned? I honestly have no idea.

to that end, the IEEE came up with the package numeric_std, which, among other things defined the unsigned and signed types, all of the usual math operations on those types, as well as functions to sign- or zero-extend vectors (resize()) and convert between signed/unsigned and integers. (No conversion function is required to convert between signed or unsigned and std_logic_vector, as they are closely-related types, and all you need is a cast.)

Of course, synthesis tools have greatly improved since the gawd-awful Synopsys FPGA Express, and we can synthesize integers and naturals without issue.

And even though numeric_std was introduced in 1995, people still write code using the Synopsys packages. And worse, the IEEE gave up and made operations on SLVs standard as part of VHDL 2008 (requiring numeric_std_unsigned and numeric_std_signed).
Title: Re: Which HDL do You Use?
Post by: NorthGuy on September 22, 2017, 09:33:55 pm
signal foo : std_logic_vector(7 downto 0);
signal bar : std_logic_vector(7 downto 0);
signal bletch : std_logic_vector(7 downto 0);

bletch <= foo + bar;


Is that operation signed or unsigned? I honestly have no idea.

The important thing is that whether it is signed or unsigned or any mix thereof, the result is exactly the same.
Title: Re: Which HDL do You Use?
Post by: romhunter on September 23, 2017, 04:26:41 am
Verilog for me. Both language feels the same, but I prefer something short since I'm a lazy ass guy. Verilog is surely shorter to write.