Counting and doing math with std_logic_vectors is to be avoided.

Why is that? I realize it takes the inclusion of a non-standard library but it sure saves a lot of casting.

Most of the tutorials I have seen use SLVs for everything.

AFAIK the numerical library was added to VHDL 'later' and so using std_logic_vector stuck with many people. But nowadays you should use numeric types because it makes a lot of things easier (like doing calculations) or use a signal as an index for an array.

The original versions of VHDL did not allow for math operations on

std_logic_vector types. You could do math on

integer,

natural and

real signals, but they weren't synthesizable (remember, this was 30 years ago!). Since most modeling was done using

std_logic and its vector form

std_logic_vector, Synopsys created a package,

std_logic_arith, to define math operations on SLVs. A problem arises, which is how to handle unsigned and signed math, and the operators and functions were defined in packages

std_logic_signed and

std_logic_unsigned.

Synopsys decided that those decidedly non-standard libraries should be included in the ieee library, which is why you see it used as

use ieee.std_logic_arith.all;instead of

use synopsys.std_logic_arith.all;and it became the defacto standard.

A glaring problem emerges: what if you need to do unsigned and signed math in the same entity? What happens when you do:

use ieee.std_logic_arith.all;

use ieee.std_logic_signed.all;

use ieee.std_logic_signed.all;and then you want to do some math:

signal foo : std_logic_vector(7 downto 0);

signal bar : std_logic_vector(7 downto 0);

signal bletch : std_logic_vector(7 downto 0);

bletch <= foo + bar;Is that operation signed or unsigned? I honestly have no idea.

to that end, the IEEE came up with the package

numeric_std, which, among other things defined the

unsigned and

signed types, all of the usual math operations on those types, as well as functions to sign- or zero-extend vectors (

resize()) and convert between

signed/

unsigned and

integers. (No conversion function is required to convert between

signed or

unsigned and

std_logic_vector, as they are closely-related types, and all you need is a cast.)

Of course, synthesis tools have greatly improved since the gawd-awful Synopsys FPGA Express, and we can synthesize integers and naturals without issue.

And even though

numeric_std was introduced in 1995, people still write code using the Synopsys packages. And worse, the IEEE gave up and made operations on SLVs standard as part of VHDL 2008 (requiring

numeric_std_unsigned and

numeric_std_signed).