Why are uC pins laid out that way?

[rea5245]

Hi,

I've been designing microcontroller circuits for several years now and I have a pet peeve: the layout of microcontroller pins. And I'd like to understand if there's a rationale behind it.

For example, I'm currently working with a PIC16F1719 (but this issue applies to every uC I've ever used). Going around the chip, there's one pin for port C, then four pins from port D, 8 pins from port B, one from port E, 5 from port A, 3 from port E, 2 from port A, 4 from port C, four from port D, and 3 from port C.

Why break up the ports like this? Why not have all of port A followed by all of port B, etc.? It would make it easier when using a port as shift register (e.g. when multiplexing LEDs and enabling each of the Common pins in sequence) or when sending a binary number (e.g. an address) out of a port.

As it is, I frequently choose pins based on their physical location, regardless of what port they belong to, to make PCB routing easy, and then I have a layer of code that converts my nice binary numbers into individual bits that I send out whichever pin it needs to go on. Am I the only one who does this, or is it common?

There must be a good reason chips are laid out in this seemingly arbitrary way. Does anyone know what it is?

Thank you,
   Bob

[T3sl4co1l]

Guessing that's just how the internal structure ended up.  I've seen it on MSP430s and STM32s too...

Doesn't make sense to me either, as I'd expect buses to be routed together internally.  Clearly they're doing something a few bits at a time, which might make more sense if you think about it: it's easier to route a couple control signals (read/write strobes) all the way across the chip, than whole chunks of buses (4-8 bits or more).

Also, I wonder if pad layout is automated along with all the other internal layout activity.  Guessing so.

I mean, that's a possible reason -- but it doesn't tell you anything about the actual internal layout and process that led to that result.

Or you can pay a premium for well-pinned devices (Atmels are usually nice?), or reconfigurable devices.  Or just fix it in software..

Tim

[tszaboo]

These micros are using the same die for different packages. For example, look at the 28 pin QFN package. Everything is in order (except RA6-7, not sure what happened there).

Same with the ST micro parts. Probably the part that you are ordering is not the BGA package, and the die is organised around the BGA package. And on the TQFP package, the leads wont be in order, otherwise bondwires would criss-cross each other.

[Ian.M]

Compare it with the pinout of the legacy PIC16C77.

For a long time Microchip have been maintaining pinout compatibility, so the PIC16F1719 pinout is upwards compatible with the legacy device and most other 40 pin 8 bit PICs.  The out-of-order port pins are nearly all shoe-horned in where the legacy device had special purpose pins like /MCLR, OSC1 and OSC2 that couldn't be used for I/O.   On newer devices, those pins are configurable between the original special purpose and I/O, offering an easy migration path for older designs.   

Microchip also keep legacy parts available far far longer than most other manufacturers, which makes them popular in more niche markets that have a long design life cycle.

[glarsson]

Another reason can be that today an eight bit port is no longer just a latch and drivers. You have PWM, AD, counters, timers, serial, USB, etc demanding chip area. Instead of trying to route all these combinations back to pins close to each other perhaps they just placed the pin close to where the port functions happened to be implemented?

[rea5245]

So basically, we all have routing problems, whether we're designing PCBs or chips.

[Ian.M]

I doubt on-chip routing has been a major pin allocation constraint for recent PIC MCUs.   Microchip's PPS (peripheral pin select) feature in recent devices goes a long way towards alleviating the peripheral routing problem on your board as it inserts a switching matrix between the peripheral modules and the Pin I/O drivers that allows you to remap many peripherals to a wide selection of different pins.   Also their recent entry level devices have limited remapping, typically between two pins on opposite sides of the chip for many peripherals, which helps routing and also helps resolve pin conflicts between different peripherals.

I suspect the split port C in the 40/44 pin packages with port D in the middle of it is due to bond wire length limitations combined with legacy on-die routing constraints.  Way back in the early days, they obviously wanted to use the same dies for both their 40 pin and 28 PICs and offer a full port C in the 28 pin package, and if they'd not spilt port C,  the high nibble would have needed much longer bond wires crossing over the die in the 28 pin package, as they probably didn't have the spare die area required to run metallisation to connect then to extra alternate bondout pads.   Its now retained for pinout compatibility reasons, and the decreased need for byte-wide parallel I/O and reduced costs for multi-layer PCBs means there is little pressure to change it by making ports remappable, similar to PPS.

[ajb]

Even looking at newer MCUs in their maximum pin count packages (inlcuding BGAs) you see the same thing.  Given the extensive muxing that larger MCUs do for peripherals you would think they could do a more sensible arrangement    Likewise the peripheral pin mapping is often totally screwy.  Some STM32F7 parts put part of the Ethernet interface right smack in the middle of the ADC pins, and the external memory interface is spread across all four sides of a 100+ pin QFP.

[westfw]

What annoys me is the chips that have, say, a 32bit GPIO Port, but are packaged in such a manner that NO full 8 bit byte is actually connected to pins...  http://www.avrfreaks.net/forum/samd10-pinout-venting

[tszaboo]

So basically, we all have routing problems, whether we're designing PCBs or chips.

It is not a problem.
I always say, it is OK for something to be difficult in engineering.
If everything would be so easy, we wouldnt have a job.

[mubes]

NXP LPC15 and LPC8 series both half configurable I/o muxes delivering the vast majority of functions to the vast majority of pins (analogue being the main exception). I know other manufacturers and chip series do it to a greater or lesser degree but the ubiquity of a full mux is a godsend....I'd like to start a one man campaign for that to be a standard feature of all CPUs, but I understand it's expensive in silicon.

[rea5245]

Muxing is for peripherals like UARTs, PWMs, I2Cs, etc. It doesn't apply to the fixed GPIO ports.

Cypress' PSoC line is, AFAIK, the most configurable microcontrollers, and even they don't let you reorder the GPIO functions. But I just looked at one of their data sheets and their GPIOs are <gasp!> in logical order: all the pins for port 0 followed by all the pins for port 1, etc!

Maybe I should consider Cypress for my next design.

- Bob

[westfw]

It is not a problem.

The "hardware group" will fix everything on the PCB.
And then the software people can fix their mistakes in SW...  :-)

[jt_eaton]

Sometimes there are issues with hi current drivers and you can't put 32  in a row  and still supply enough current to switch all of them at the same time.

I don't think anyone would design a IC without doing a layout and reference design.

[MT]

On chip florplaning and routing for peripherals used to be a thankless job and i assume still are.