I have just got some FPGA boards back from the fab and am just trying to bring them up by controlling the LED. But for some reason it's not doing what I want.
I am using an iCE40HX8K in the 121 bga package and lattice Diamond programmer and iCECube2. Schematic attached. It programs fine via a FT2232H mini module and the done pin asserts after I program it. I can read back the program and verify that it is programmed correctly.
(Of the components shown in the schematic, everything is stuffed except C502, C505, C504, C506 which should be fine as I'm not using a PLL yet).
My Verilog code:
module main(output LED, output DEBUG7);
assign LED = 1;
assign DEBUG7 = 1;
endmodule
My constraints file:
set_io DEBUG7 E2 -pullup no
set_io LED J8 -pullup no
The LED D102 should turn on after programming but it doesn't. I've measured the voltage across D102 and it's around 900mV, regardless of whether I set LED = 0 or LED = 1.
D102 does turn on if I turn on the internal pull-up however I then cannot turn it off! D102 is also on pre-configuration because the pull-ups are engaged, but turns off once I program the FPGA.
(Everything I've said here is also true for pin DEBUG7). 3V3 and 1V2 rails are fine.
I'm hoping I'm doing something stupid...
Here is the log from iCECube2:
"C:\lscc\iCEcube2.2017.08\sbt_backend\bin\win32\opt\synpwrap\synpwrap.exe" -prj "TestHP2VGA_syn.prj" -log "TestHP2VGA_Implmnt/TestHP2VGA.srr"
Copyright (C) 1992-2014 Lattice Semiconductor Corporation. All rights reserved.
==contents of TestHP2VGA_Implmnt/TestHP2VGA.srr
#Build: Synplify Pro L-2016.09L+ice40, Build 077R, Dec 2 2016
#install: C:\lscc\iCEcube2.2017.08\synpbase
#OS: Windows 8 6.2
#Hostname: DESKTOP-6I79T4A
# Wed Aug 22 20:30:08 2018
#Implementation: TestHP2VGA_Implmnt
Synopsys HDL Compiler, version comp2016q3p1, Build 141R, built Dec 5 2016
@N|Running in 64-bit mode
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
Synopsys Verilog Compiler, version comp2016q3p1, Build 141R, built Dec 5 2016
@N|Running in 64-bit mode
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
@I::"C:\lscc\iCEcube2.2017.08\synpbase\lib\generic\sb_ice40.v" (library work)
@I::"C:\lscc\iCEcube2.2017.08\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__)
@I::"C:\lscc\iCEcube2.2017.08\synpbase\lib\vlog\umr_capim.v" (library snps_haps)
@I::"C:\lscc\iCEcube2.2017.08\synpbase\lib\vlog\scemi_objects.v" (library snps_haps)
@I::"C:\lscc\iCEcube2.2017.08\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
@I::"C:\Users\Matt\Downloads\main.v" (library work)
Verilog syntax check successful!
File C:\Users\Matt\Downloads\main.v changed - recompiling
Selecting top level module main
@N: CG364 :"C:\Users\Matt\Downloads\main.v":1:7:1:10|Synthesizing module main in library work.
At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 69MB peak: 70MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
Process completed successfully.
# Wed Aug 22 20:30:09 2018
###########################################################]
Synopsys Netlist Linker, version comp2016q3p1, Build 141R, built Dec 5 2016
@N|Running in 64-bit mode
@N: NF107 :"C:\Users\Matt\Downloads\main.v":1:7:1:10|Selected library: work cell: main view verilog as top level
@N: NF107 :"C:\Users\Matt\Downloads\main.v":1:7:1:10|Selected library: work cell: main view verilog as top level
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
Process completed successfully.
# Wed Aug 22 20:30:09 2018
###########################################################]
@END
At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
Process completed successfully.
# Wed Aug 22 20:30:09 2018
###########################################################]
Synopsys Netlist Linker, version comp2016q3p1, Build 141R, built Dec 5 2016
@N|Running in 64-bit mode
File C:\Users\Matt\Downloads\TestHP2VGA\TestHP2VGA_Implmnt\synwork\TestHP2VGA_comp.srs changed - recompiling
@N: NF107 :"C:\Users\Matt\Downloads\main.v":1:7:1:10|Selected library: work cell: main view verilog as top level
@N: NF107 :"C:\Users\Matt\Downloads\main.v":1:7:1:10|Selected library: work cell: main view verilog as top level
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
Process completed successfully.
# Wed Aug 22 20:30:10 2018
###########################################################]
Pre-mapping Report
# Wed Aug 22 20:30:11 2018
Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1612R, Built Dec 5 2016 10:31:39
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
Product Version L-2016.09L+ice40
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)
@A: MF827 |No constraint file specified.
@L: C:\Users\Matt\Downloads\TestHP2VGA\TestHP2VGA_Implmnt\TestHP2VGA_scck.rpt
Printing clock summary report in "C:\Users\Matt\Downloads\TestHP2VGA\TestHP2VGA_Implmnt\TestHP2VGA_scck.rpt" file
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
ICG Latch Removal Summary:
Number of ICG latches removed: 0
Number of ICG latches not removed: 0
syn_allowed_resources : blockrams=32 set on top level netlist main
Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB)
Clock Summary
*****************
Start Requested Requested Clock Clock Clock
Clock Frequency Period Type Group Load
---------------------------------------------------------------
===============================================================
Finished Pre Mapping Phase.
@N: BN225 |Writing default property annotation file C:\Users\Matt\Downloads\TestHP2VGA\TestHP2VGA_Implmnt\TestHP2VGA.sap.
Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB)
None
None
Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB)
Pre-mapping successful!
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 46MB peak: 133MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Wed Aug 22 20:30:12 2018
###########################################################]
Map & Optimize Report
# Wed Aug 22 20:30:12 2018
Synopsys Lattice Technology Mapper, Version maplat, Build 1612R, Built Dec 5 2016 10:31:39
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
Product Version L-2016.09L+ice40
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB)
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB)
Available hyper_sources - for debug and ip models
None Found
@N: MT206 |Auto Constrain mode is enabled
Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 130MB peak: 133MB)
Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 130MB peak: 133MB)
Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 130MB peak: 133MB)
Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 130MB peak: 133MB)
Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 130MB peak: 133MB)
Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 130MB peak: 133MB)
Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 130MB peak: 133MB)
Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 130MB peak: 133MB)
Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 130MB peak: 133MB)
Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 130MB peak: 133MB)
Pass CPU time Worst Slack Luts / Registers
------------------------------------------------------------
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 130MB peak: 133MB)
Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 130MB peak: 133MB)
@S |Clock Optimization Summary
#### START OF CLOCK OPTIMIZATION REPORT #####[
0 non-gated/non-generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
0 instances converted, 0 sequential instances remain driven by gated/generated clocks
##### END OF CLOCK OPTIMIZATION REPORT ######]
Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 105MB peak: 133MB)
Writing Analyst data base C:\Users\Matt\Downloads\TestHP2VGA\TestHP2VGA_Implmnt\synwork\TestHP2VGA_m.srm
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 129MB peak: 133MB)
Writing EDIF Netlist and constraint files
@N: BW103 |The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns.
@N: BW107 |Synopsys Constraint File capacitance units using default value of 1pF
@N: FX1056 |Writing EDF file: C:\Users\Matt\Downloads\TestHP2VGA\TestHP2VGA_Implmnt\TestHP2VGA.edf
L-2016.09L+ice40
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 130MB peak: 133MB)
Start final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 131MB peak: 133MB)
##### START OF TIMING REPORT #####[
# Timing Report written on Wed Aug 22 20:30:14 2018
#
Top view: main
Requested Frequency: 1.0 MHz
Wire load mode: top
Paths requested: 5
Constraint File(s):
@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
Performance Summary
*******************
Worst slack in design: NA
Clock Relationships
*******************
Clocks | rise to rise | fall to fall | rise to fall | fall to rise
--------------------------------------------------------------------------------------------------------
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
--------------------------------------------------------------------------------------------------------
========================================================================================================
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
Interface Information
*********************
No IO constraint found
##### END OF TIMING REPORT #####]
Timing exceptions that could not be applied
None
Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 131MB peak: 133MB)
Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 131MB peak: 133MB)
---------------------------------------
Resource Usage Report for main
Mapping to part: ice40hx8kct256
Cell usage:
SB_LUT4 0 uses
I/O ports: 2
I/O primitives: 2
SB_IO 2 uses
I/O Register bits: 0
Register bits not including I/Os: 0 (0%)
Total load per clock:
@S |Mapping Summary:
Total LUTs: 0 (0%)
Mapper successful!
At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 25MB peak: 133MB)
Process took 0h:00m:02s realtime, 0h:00m:02s cputime
# Wed Aug 22 20:30:15 2018
###########################################################]
Synthesis exit by 0.
Current Implementation TestHP2VGA_Implmnt its sbt path: C:/Users/Matt/Downloads/TestHP2VGA/TestHP2VGA_Implmnt\sbt
Synthesis succeeded.
Synthesis runtime 9 seconds
"C:/lscc/iCEcube2.2017.08/sbt_backend/bin/win32/opt\edifparser.exe" "C:\lscc\iCEcube2.2017.08\sbt_backend\devices\ICE40P08.dev" "C:/Users/Matt/Downloads/TestHP2VGA/TestHP2VGA_Implmnt/TestHP2VGA.edf " "C:/Users/Matt/Downloads/TestHP2VGA/TestHP2VGA_Implmnt\sbt\netlist" "-pBG121" "-yC:/Users/Matt/Downloads/TestHP2VGA/TestHP2VGA_Implmnt/sbt/constraint/main_pcf_sbt.pcf " -c --devicename iCE40HX8K
Lattice Semiconductor Corporation Edif Parser
Release: 2017.08.27940
Build Date: Sep 11 2017 16:51:25
Parsing edif file: C:/Users/Matt/Downloads/TestHP2VGA/TestHP2VGA_Implmnt/TestHP2VGA.edf...
Parsing constraint file: C:/Users/Matt/Downloads/TestHP2VGA/TestHP2VGA_Implmnt/sbt/constraint/main_pcf_sbt.pcf ...
start to read sdc/scf file C:/Users/Matt/Downloads/TestHP2VGA/TestHP2VGA_Implmnt/TestHP2VGA.scf
sdc_reader OK C:/Users/Matt/Downloads/TestHP2VGA/TestHP2VGA_Implmnt/TestHP2VGA.scf
Stored edif netlist at C:/Users/Matt/Downloads/TestHP2VGA/TestHP2VGA_Implmnt\sbt\netlist\oadb-main...
write Timing Constraint to C:/Users/Matt/Downloads/TestHP2VGA/TestHP2VGA_Implmnt\sbt/Temp/sbt_temp.sdc
EDIF Parser succeeded
Top module is: main
EDF Parser run-time: 1 (sec)
"C:/lscc/iCEcube2.2017.08/sbt_backend/bin/win32/opt\sbtplacer.exe" --des-lib "C:/Users/Matt/Downloads/TestHP2VGA/TestHP2VGA_Implmnt\sbt\netlist\oadb-main" --outdir "C:/Users/Matt/Downloads/TestHP2VGA/TestHP2VGA_Implmnt\sbt\outputs\placer" --device-file "C:\lscc\iCEcube2.2017.08\sbt_backend\devices\ICE40P08.dev" --package BG121 --deviceMarketName iCE40HX8K --sdc-file "C:/Users/Matt/Downloads/TestHP2VGA/TestHP2VGA_Implmnt\sbt\Temp/sbt_temp.sdc" --lib-file "C:\lscc\iCEcube2.2017.08\sbt_backend\devices\ice40HX8K.lib" --effort_level std --out-sdc-file "C:/Users/Matt/Downloads/TestHP2VGA/TestHP2VGA_Implmnt\sbt\outputs\placer\main_pl.sdc"
Executing : C:\lscc\iCEcube2.2017.08\sbt_backend\bin\win32\opt\sbtplacer.exe --des-lib C:/Users/Matt/Downloads/TestHP2VGA/TestHP2VGA_Implmnt\sbt\netlist\oadb-main --outdir C:/Users/Matt/Downloads/TestHP2VGA/TestHP2VGA_Implmnt\sbt\outputs\placer --device-file C:\lscc\iCEcube2.2017.08\sbt_backend\devices\ICE40P08.dev --package BG121 --deviceMarketName iCE40HX8K --sdc-file C:/Users/Matt/Downloads/TestHP2VGA/TestHP2VGA_Implmnt\sbt\Temp/sbt_temp.sdc --lib-file C:\lscc\iCEcube2.2017.08\sbt_backend\devices\ice40HX8K.lib --effort_level std --out-sdc-file C:/Users/Matt/Downloads/TestHP2VGA/TestHP2VGA_Implmnt\sbt\outputs\placer\main_pl.sdc
Lattice Semiconductor Corporation Placer
Release: 2017.08.27940
Build Date: Sep 11 2017 17:12:23
I2004: Option and Settings Summary
=============================================================
Device file - C:\lscc\iCEcube2.2017.08\sbt_backend\devices\ICE40P08.dev
Package - BG121
Design database - C:/Users/Matt/Downloads/TestHP2VGA/TestHP2VGA_Implmnt\sbt\netlist\oadb-main
SDC file - C:/Users/Matt/Downloads/TestHP2VGA/TestHP2VGA_Implmnt\sbt\Temp/sbt_temp.sdc
Output directory - C:/Users/Matt/Downloads/TestHP2VGA/TestHP2VGA_Implmnt\sbt\outputs\placer
Timing library - C:\lscc\iCEcube2.2017.08\sbt_backend\devices\ice40HX8K.lib
Effort level - std
I2050: Starting reading inputs for placer
=============================================================
I2100: Reading design library: C:/Users/Matt/Downloads/TestHP2VGA/TestHP2VGA_Implmnt\sbt\netlist\oadb-main/BFPGA_DESIGN_ep
I2065: Reading device file : C:\lscc\iCEcube2.2017.08\sbt_backend\devices\ICE40P08.dev
I2051: Reading of inputs for placer completed successfully
I2053: Starting placement of the design
=============================================================
Input Design Statistics
Number of LUTs : 0
Number of DFFs : 0
Number of DFFs packed to IO : 0
Number of Carrys : 0
Number of RAMs : 0
Number of ROMs : 0
Number of IOs : 2
Number of GBIOs : 0
Number of GBs : 0
Number of WarmBoot : 0
Number of PLLs : 0
Phase 1
I2077: Start design legalization
Design Legalization Statistics
Number of feedthru LUTs inserted to legalize input of DFFs : 0
Number of feedthru LUTs inserted for LUTs driving multiple DFFs : 0
Number of LUTs replicated for LUTs driving multiple DFFs : 0
Number of feedthru LUTs inserted to legalize output of CARRYs : 0
Number of feedthru LUTs inserted to legalize global signals : 0
Number of feedthru CARRYs inserted to legalize input of CARRYs : 0
Number of inserted LUTs to Legalize IOs with PIN_TYPE= 01xxxx : 0
Number of inserted LUTs to Legalize IOs with PIN_TYPE= 10xxxx : 0
Number of inserted LUTs to Legalize IOs with PIN_TYPE= 11xxxx : 0
Total LUTs inserted : 0
Total CARRYs inserted : 0
I2078: Design legalization is completed successfully
I2088: Phase 1, elapsed time : 0.0 (sec)
Phase 2
I2088: Phase 2, elapsed time : 0.1 (sec)
Phase 3
Design Statistics after Packing
Number of LUTs : 1
Number of DFFs : 0
Number of DFFs packed to IO : 0
Number of Carrys : 0
Device Utilization Summary after Packing
Sequential LogicCells
LUT and DFF : 0
LUT, DFF and CARRY : 0
Combinational LogicCells
Only LUT : 1
CARRY Only : 0
LUT with CARRY : 0
LogicCells : 1/7680
PLBs : 1/960
BRAMs : 0/32
IOs and GBIOs : 2/93
PLLs : 0/2
I2088: Phase 3, elapsed time : 0.4 (sec)
Phase 4
W2659: No Constrained paths were found. The placer will run in non-timing driven mode.
I2088: Phase 4, elapsed time : 0.4 (sec)
Phase 5
I2088: Phase 5, elapsed time : 0.0 (sec)
Phase 6
I2088: Phase 6, elapsed time : 0.0 (sec)
Final Design Statistics
Number of LUTs : 1
Number of DFFs : 0
Number of DFFs packed to IO : 0
Number of Carrys : 0
Number of RAMs : 0
Number of ROMs : 0
Number of IOs : 2
Number of GBIOs : 0
Number of GBs : 0
Number of WarmBoot : 0
Number of PLLs : 0
Device Utilization Summary
LogicCells : 1/7680
PLBs : 1/960
BRAMs : 0/32
IOs and GBIOs : 2/93
PLLs : 0/2
I2054: Placement of design completed successfully
I2076: Placer run-time: 2.2 sec.
"C:/lscc/iCEcube2.2017.08/sbt_backend/bin/win32/opt\packer.exe" "C:\lscc\iCEcube2.2017.08\sbt_backend\devices\ICE40P08.dev" "C:/Users/Matt/Downloads/TestHP2VGA/TestHP2VGA_Implmnt\sbt\netlist\oadb-main" --package BG121 --outdir "C:/Users/Matt/Downloads/TestHP2VGA/TestHP2VGA_Implmnt\sbt\outputs\packer" --DRC_only --translator "C:\lscc\iCEcube2.2017.08\sbt_backend\bin\sdc_translator.tcl" --src_sdc_file "C:/Users/Matt/Downloads/TestHP2VGA/TestHP2VGA_Implmnt\sbt\outputs\placer\main_pl.sdc" --dst_sdc_file "C:/Users/Matt/Downloads/TestHP2VGA/TestHP2VGA_Implmnt\sbt\outputs\packer\main_pk.sdc" --devicename iCE40HX8K
Lattice Semiconductor Corporation Packer
Release: 2017.08.27940
Build Date: Sep 11 2017 16:52:47
Begin Packing...
initializing finish
Total HPWL cost is 42
used logic cells: 1
Design Rule Checking Succeeded
DRC Checker run-time: 1 (sec)
"C:/lscc/iCEcube2.2017.08/sbt_backend/bin/win32/opt\packer.exe" "C:\lscc\iCEcube2.2017.08\sbt_backend\devices\ICE40P08.dev" "C:/Users/Matt/Downloads/TestHP2VGA/TestHP2VGA_Implmnt\sbt\netlist\oadb-main" --package BG121 --outdir "C:/Users/Matt/Downloads/TestHP2VGA/TestHP2VGA_Implmnt\sbt\outputs\packer" --translator "C:\lscc\iCEcube2.2017.08\sbt_backend\bin\sdc_translator.tcl" --src_sdc_file "C:/Users/Matt/Downloads/TestHP2VGA/TestHP2VGA_Implmnt\sbt\outputs\placer\main_pl.sdc" --dst_sdc_file "C:/Users/Matt/Downloads/TestHP2VGA/TestHP2VGA_Implmnt\sbt\outputs\packer\main_pk.sdc" --devicename iCE40HX8K
Lattice Semiconductor Corporation Packer
Release: 2017.08.27940
Build Date: Sep 11 2017 16:52:47
Begin Packing...
initializing finish
Total HPWL cost is 42
used logic cells: 1
Translating sdc file C:/Users/Matt/Downloads/TestHP2VGA/TestHP2VGA_Implmnt\sbt\outputs\placer\main_pl.sdc...
Translated sdc file is C:/Users/Matt/Downloads/TestHP2VGA/TestHP2VGA_Implmnt\sbt\outputs\packer\main_pk.sdc
Packer succeeded
Packer run-time: 1 (sec)
"C:\lscc\iCEcube2.2017.08\sbt_backend\bin\win32\opt\sbrouter.exe" "C:\lscc\iCEcube2.2017.08\sbt_backend\devices\ICE40P08.dev" "C:\Users\Matt\Downloads\TestHP2VGA\TestHP2VGA_Implmnt\sbt\netlist\oadb-main" "C:\lscc\iCEcube2.2017.08\sbt_backend\devices\ice40HX8K.lib" "C:\Users\Matt\Downloads\TestHP2VGA\TestHP2VGA_Implmnt\sbt\outputs\packer\main_pk.sdc" --outdir "C:\Users\Matt\Downloads\TestHP2VGA\TestHP2VGA_Implmnt\sbt\outputs\router" --sdf_file "C:/Users/Matt/Downloads/TestHP2VGA/TestHP2VGA_Implmnt\sbt\outputs\simulation_netlist\main_sbt.sdf" --pin_permutation
SJRouter....
Executing : C:\lscc\iCEcube2.2017.08\sbt_backend\bin\win32\opt\sbrouter.exe C:\lscc\iCEcube2.2017.08\sbt_backend\devices\ICE40P08.dev C:\Users\Matt\Downloads\TestHP2VGA\TestHP2VGA_Implmnt\sbt\netlist\oadb-main C:\lscc\iCEcube2.2017.08\sbt_backend\devices\ice40HX8K.lib C:\Users\Matt\Downloads\TestHP2VGA\TestHP2VGA_Implmnt\sbt\outputs\packer\main_pk.sdc --outdir C:\Users\Matt\Downloads\TestHP2VGA\TestHP2VGA_Implmnt\sbt\outputs\router --sdf_file C:/Users/Matt/Downloads/TestHP2VGA/TestHP2VGA_Implmnt\sbt\outputs\simulation_netlist\main_sbt.sdf --pin_permutation
Lattice Semiconductor Corporation Router
Release: 2017.08.27940
Build Date: Sep 11 2017 17:02:50
I1203: Reading Design main
Read design time: 0
I1202: Reading Architecture of device iCE40HX8K
Read device time: 16
I1209: Started routing
I1223: Total Nets : 1
I1212: Iteration 1 : 0 unrouted : 0 seconds
I1215: Routing is successful
Routing time: 1
I1206: Completed routing
I1204: Writing Design main
Lib Closed
I1210: Writing routes
I1218: Exiting the router
I1224: Router run-time : 17 seconds
"C:/lscc/iCEcube2.2017.08/sbt_backend/bin/win32/opt\netlister.exe" --verilog "C:/Users/Matt/Downloads/TestHP2VGA/TestHP2VGA_Implmnt\sbt\outputs\simulation_netlist\main_sbt.v" --vhdl "C:/Users/Matt/Downloads/TestHP2VGA/TestHP2VGA_Implmnt/sbt/outputs/simulation_netlist\main_sbt.vhd" --lib "C:/Users/Matt/Downloads/TestHP2VGA/TestHP2VGA_Implmnt\sbt\netlist\oadb-main" --view rt --device "C:\lscc\iCEcube2.2017.08\sbt_backend\devices\ICE40P08.dev" --splitio --in-sdc-file "C:/Users/Matt/Downloads/TestHP2VGA/TestHP2VGA_Implmnt\sbt\outputs\packer\main_pk.sdc" --out-sdc-file "C:/Users/Matt/Downloads/TestHP2VGA/TestHP2VGA_Implmnt\sbt\outputs\netlister\main_sbt.sdc"
Lattice Semiconductor Corporation Verilog & VHDL Netlister
Release: 2017.08.27940
Build Date: Sep 11 2017 17:30:26
Generating Verilog & VHDL netlist files ...
Writing C:/Users/Matt/Downloads/TestHP2VGA/TestHP2VGA_Implmnt\sbt\outputs\simulation_netlist\main_sbt.v
Writing C:/Users/Matt/Downloads/TestHP2VGA/TestHP2VGA_Implmnt/sbt/outputs/simulation_netlist\main_sbt.vhd
Netlister succeeded.
Netlister run-time: 1 (sec)
"C:/lscc/iCEcube2.2017.08/sbt_backend/bin/win32/opt\sbtimer.exe" --des-lib "C:/Users/Matt/Downloads/TestHP2VGA/TestHP2VGA_Implmnt\sbt\netlist\oadb-main" --lib-file "C:\lscc\iCEcube2.2017.08\sbt_backend\devices\ice40HX8K.lib" --sdc-file "C:/Users/Matt/Downloads/TestHP2VGA/TestHP2VGA_Implmnt\sbt\outputs\netlister\main_sbt.sdc" --sdf-file "C:/Users/Matt/Downloads/TestHP2VGA/TestHP2VGA_Implmnt\sbt\outputs\simulation_netlist\main_sbt.sdf" --report-file "C:\Users\Matt\Downloads\TestHP2VGA\TestHP2VGA_Implmnt\sbt\outputs\timer\main_timing.rpt" --device-file "C:\lscc\iCEcube2.2017.08\sbt_backend\devices\ICE40P08.dev" --timing-summary
Executing : C:\lscc\iCEcube2.2017.08\sbt_backend\bin\win32\opt\sbtimer.exe --des-lib C:/Users/Matt/Downloads/TestHP2VGA/TestHP2VGA_Implmnt\sbt\netlist\oadb-main --lib-file C:\lscc\iCEcube2.2017.08\sbt_backend\devices\ice40HX8K.lib --sdc-file C:/Users/Matt/Downloads/TestHP2VGA/TestHP2VGA_Implmnt\sbt\outputs\netlister\main_sbt.sdc --sdf-file C:/Users/Matt/Downloads/TestHP2VGA/TestHP2VGA_Implmnt\sbt\outputs\simulation_netlist\main_sbt.sdf --report-file C:\Users\Matt\Downloads\TestHP2VGA\TestHP2VGA_Implmnt\sbt\outputs\timer\main_timing.rpt --device-file C:\lscc\iCEcube2.2017.08\sbt_backend\devices\ICE40P08.dev --timing-summary
Lattice Semiconductor Corporation Timer
Release: 2017.08.27940
Build Date: Sep 11 2017 17:01:05
Timer run-time: 1 seconds
timer succeeded.
"C:/lscc/iCEcube2.2017.08/sbt_backend/bin/win32/opt\bitmap.exe" "C:\lscc\iCEcube2.2017.08\sbt_backend\devices\ICE40P08.dev" --design "C:/Users/Matt/Downloads/TestHP2VGA/TestHP2VGA_Implmnt\sbt\netlist\oadb-main" --device_name iCE40HX8K --package BG121 --outdir "C:/Users/Matt/Downloads/TestHP2VGA/TestHP2VGA_Implmnt\sbt\outputs\bitmap" --low_power on --init_ram on --init_ram_bank 1111 --frequency low --warm_boot on
Lattice Semiconductor Corporation Bit Stream Generator
Release: 2017.08.27940
Build Date: Sep 11 2017 17:29:39
Bit Stream File Size: 1080760 (1M 31K 440 Bits)
Bit Stream Generator succeeded
Bitmap run-time: 1 (sec)
Please spot my mistake!