Why use hardened SPI?

[MattHollands]

I am using a Lattice iCE40 Ultra FPGA which has 2 hardened SPI and 2 hardened I2C busses and I was kind of surprised to see a hardened SPI bus. A SPI bus can be as simple as a shift register driven by the SCK pin - and I feel like it is easier to just write your own IP, than it is to figure out the register structure of their implementation and use theirs.  (I2C has weird things like clock stretching which sounds annoying to implement so I am focusing on SPI).

Reasons I can see for using their IP:
- If you want it to work with unknown third party SPI devices so you have to make sure that the standard is fully implemented
- You have multiple masters and need to handle bus arbitration etc.

However, I expect that the majority case is using a SPI bus with only a single master and known slaves (with known features) and in this case it seems easier to write my own bus controller. My application uses a single Master and Slave to transfer an image between devices.

I guess my question is - am I overlooking something? Am I being lazy by not properly learning how to use their IP? Would you write your own or use theirs?

Here is their SPI IP usage guide:
http://latticesemi.com/view_document?document_id=50117

[rstofer]

I wrote my own SPI interface for a known peripheral.  That way I could get the CPOL and CPHA correct.  But I knew what device I planned to connect so I didn't provide for a register that would allow me to change configurations.  I also didn't worry about interrupts, all the device needed to do was send out some 8 bit bytes at about 11 MHz.

It looks to me like if you are using IP for the CPU, you probably should use IP for the peripherals.

[nctnico]

I'd use existing blocks as much as possible but sometimes they be buggy (or non working) depending on where they came from. It is unclear to me what Lattice means with 'hardened IP'. I'd try to figure that out first and if it means 'well tested' then use Lattice's IP because much of the stuff you'll find for free will be less reliable.

[Ice-Tea]

Might have something to do with the fact they can be configured through SPI and they figured 'hey, if we need that hardcoded block anyways for configuration, might as well turn it into a 'feature''.

[MattHollands]

It looks to me like if you are using IP for the CPU, you probably should use IP for the peripherals.

I am not using a CPU at all.

It is unclear to me what Lattice means with 'hardened IP'.

Doesn't it just mean that there is hardware there that is designed to work as a SPI bus as opposed to part of the fabric?

Might have something to do with the fact they can be configured through SPI and they figured 'hey, if we need that hardcoded block anyways for configuration, might as well turn it into a 'feature''.

Yeah that actually makes a lot of sense.

[nctnico]

To me 'hardened' means something has been enhanced to be durable and resillient. That doesn't match with hardcoded IP or something like that. Also there is also an I2C interface. Again: I'd search or ask Lattice what their salesdroids have been smoking when they decided to use the word 'hardened' and go from there.

[rstofer]

To me 'hardened' means something has been enhanced to be durable and resillient. That doesn't match with hardcoded IP or something like that. Also there is also an I2C interface. Again: I'd search or ask Lattice what their salesdroids have been smoking when they decided to use the word 'hardened' and go from there.

In FPGA world, that's called radiation tolerant (RT). "Hardened" in FPGA world simply means IP implemented in hardwired silicon connection, not programmable soft cores.

So, does that mean it's actually implemented in silicon?  If so, how many instantiations can I have?  That would be pretty neat having some building blocks already implemented.  The problem is, there will always be an assumed bus structure which, at least in my case, makes absolutely no sense.

[MattHollands]

It has 2 I2C blocks and 2 SPI blocks. Ie 2 instantiations of each.

[mikerj]

So, does that mean it's actually implemented in silicon?  If so, how many instantiations can I have?  That would be pretty neat having some building blocks already implemented.  The problem is, there will always be an assumed bus structure which, at least in my case, makes absolutely no sense.

You can only instantiate peripherals that are held in the fabric.  If you have a peripheral hard wired in silicon, how could you possibly instantiate more of them?

[rstofer]

So, does that mean it's actually implemented in silicon?  If so, how many instantiations can I have?  That would be pretty neat having some building blocks already implemented.  The problem is, there will always be an assumed bus structure which, at least in my case, makes absolutely no sense.

You can only instantiate peripherals that are held in the fabric.  If you have a peripheral hard wired in silicon, how could you possibly instantiate more of them?

I didn't suspect I could!  I'm surprised it is being done at all.  Still, most FPGAs need something like SPI to boot so I suppose it makes sense to have a peripheral in silicon.

[stfsux]

Using an IP is kewl, save times, etc. but If you suddenly need to switch from an other FPGA brand (or even an other FPGA from the same brand) you will be screw up.
And as you said, SPI is quite simple to write in any HDL and it has the annoying fact that SPI is not a standard but a de facto one.
So I would suggest you to stay on your own IP.

[mark03]

"Hardened" is a stupid word in this context, further proof that humans prefer longer and more verbose language to get the same point across, all else being equal.  (They should properly be called "hard" blocks; "hardened" makes it sound like Lattice has a magical process for "freezing" programmable logic into a hardened state.)

[julian1]

Is it possible that the bitstream for the spi is defined in the one-time programmable NVCM? So it has properties of both hardware and software - leading marketers towards the  'hardened' terminology?