Xilinx Spartan 7 seen

[NorthGuy]

It's not that simple. For memory interfaces there are quite strict rules as to which pins can be used. I haven't actually tried making a MIG design with 484 pin part to see if I can get away with only using pins from 3 outer "layers" of pins, but my gut feeling suggests it won't be possible because most DQ groups contain pins that are "deeper" than outer 3 rows, and you can only user pins from the single bank column for controller.

On a stock 4-layer boards, the pre-peg is usually quite thick, so laying 50-Ohm traces on the top layer is impractical - they would have to be too wide. So, you would have to go to layer 2 or 3, which means you only have dog-bones on the top layer. If you select pins which are 3-5 rows deep into FPGA, it should work quite well. It is not that difficult to fan out a group of adjacent pins (2*DQS + 8*DQ and may be 1*DM) in one layer. I guess, even if you had 10-layer board you would do it in one layer anyway.

[asmi]

On a stock 4-layer boards, the pre-peg is usually quite thick, so laying 50-Ohm traces on the top layer is impractical - they would have to be too wide.

This is not necessarily the case. Infact, if you order 1.2 mm thick 4 layer boards from PCBWay, they will use 0.13 mm prepreg (full stackup is 0.035 Cu/0.13 PP/0.035 Cu/0.73 Core/0.035 Cu/0.13 PP/0.035 Cu), which means 50 Ohm traces are quite narrow at ~0.225 mm. That is what I've done for my board with HyperRAM chips as they operate at 166 MHz DDR (so DQ lines switch at 333 MHz), and it works with no problems on a real board. Of course in breakout areas I had to use minimal-width 0.15 mm traces, but this is universally recommended practice as there is simply no other way to do it.
Currently I'm trying to see if I can route FPGA + DDR3 on a 4-layer board with 0.125/0.125/0.25 process, already attempted a couple times, but failed But now I'm much better quipped to do that tools-wise, so I'm hopeful I would be able to get it done and the board will actually work

[Scrts]

On a stock 4-layer boards, the pre-peg is usually quite thick, so laying 50-Ohm traces on the top layer is impractical - they would have to be too wide.

This is not necessarily the case. Infact, if you order 1.2 mm thick 4 layer boards from PCBWay, they will use 0.13 mm prepreg (full stackup is 0.035 Cu/0.13 PP/0.035 Cu/0.73 Core/0.035 Cu/0.13 PP/0.035 Cu), which means 50 Ohm traces are quite narrow at ~0.225 mm. That is what I've done for my board with HyperRAM chips as they operate at 166 MHz DDR (so DQ lines switch at 333 MHz), and it works with no problems on a real board. Of course in breakout areas I had to use minimal-width 0.15 mm traces, but this is universally recommended practice as there is simply no other way to do it.
Currently I'm trying to see if I can route FPGA + DDR3 on a 4-layer board with 0.125/0.125/0.25 process, already attempted a couple times, but failed But now I'm much better quipped to do that tools-wise, so I'm hopeful I would be able to get it done and the board will actually work

You will most likely have power/gnd integrity issues with a 4 layer board and FPGA+DDR3. If the power will float, then the signal condition doesn't even matter...

[asmi]

You will most likely have power/gnd integrity issues with a 4 layer board and FPGA+DDR3. If the power will float, then the signal condition doesn't even matter...

Why would you think it would float on 4 layer board, but not on 6 layer one? What does it have to do with amount of layers? I'm just learning the ropes, so I'd appreciate more details on this.