Interesting they work to a HLL and readable approach but use a 2 process model, which loses a lot of the HLL features available in VHDL but keeps your register stages clear. The synthesiser will rip that sort of strict design apart if allowed to replicate paths and push/pull registers. Their final FPGA utilisation results aren't fantastic but its not been optimised heavily for those targets so it may do very well in ASICs, once its more widespread a heavily FPGA optimised version could be worthwhile.