2CH 50MHz AWG based on AD9102

[David Chamberlain]

--- WARNING ---

While I have built and tested many features of this design it is after all a prototype in the true sense of the word. The SMP and digital 3V3 supplies are not enough, I messed up the Ethernet interface and several other issues exist in the linked documents below. Please do not use these as reference designs. You have been warned.

--- On with the show ---

Hi All,

I decided a year back to make my own AWG based on the AD9102. The main aim was to explore a few things that I had not had much exposure to in my professional career such as differential clocking and signaling.

So what is it? A 2 channel arbitrary wave form generator with 10Hz steps from DC to 50MHz. I really wanted to go down to DC for some digital rf immunity tests I want to do later (even though buying a commercial ARB would have taken less time and money). It has two inputs. The first is for an external 10MHz reference source that can be used to drive the DAC's or to calibrate the on board VCXO or optional (read more expensive) OCXO. The second input is dedicated to frequency counting. Positive and Negative rails of switching power supply are trim-able via digital pots as is the XO.

My original rant regarding assembly of the board is here.
https://www.eevblog.com/forum/projects/brain-mud/msg1213672/

Now that I have gotten past a few hurdles in this design I thought I would share schematics and some thoughts on the project. I'll drip feed stuff on this thread as I make more progress, and am happy to answer questions or take feedback.

When starting out I thought "hey! why is so little information available on the web for this chip? Surely many other DIY'ers have beaten this thing to death already" The best I can make out it's 4 years old at least.

Well the best I can figure is the documentation is appalling with numerous errors and contradictions. I think it is best summed up with this poor engineers experience.
https://ez.analog.com/thread/35554

Another reason may be the limited SRAM size of 4096 samples or the differential signaling?

The best I can tell the datasheet has still not been updated. So I might have been put off unless I was ignorant of that information before I had already committed to doing the design, and here I am and happy to say it's been worthwhile.

The AD9102 is the single channel version of the four channel AD9106. It has a 14bit resolution with a max clock of 180MHz giving the best case 90MHz square wave output. My design aims for the weird and hard to accurately achieve 167776160 Hz to give the 10Hz steps. However as the PLL on board can be reconfigured by the MCU you can set it up for anything you like. In fact when I first got it running the PLL was at 20MHz and generating a good looking sine wave with no problem.

The chip has a few interesting things going for it. First it has a dedicated sine waves generator, a dedicated triangle wave generator, sudo random noise generator (who cares), constant DC output set to the 14 bit resolution (again who cares), 4096x14bit SRAM for DDS. The cool stuff happens with the mux section where the sine wave can be amplitude modulated with SRAM patterns or Frequency modulated.

My design runs on the ATSAM4E16 Cortex M4 has RS232, Ethernet and USB (borrowed with thanks from the Atmel reference designs) and is running FreeRTOS.

The current status of the project is as follows.
1) Board powers up and does not catch on fire - check
2) PLL locks to desired frequency - check.
3) Clock distribution good - check
4) SPI can talk to all chips - check
5) AD9102 outputs sine wave up to 50MHz - check but it's suffering due to low number of samples at that frequency.
6) AD9102 outputs SRAM AWF - check.

Each output is amplified (x15) with a single THS3091 current feedback opamp converting the differential signal to single ended. Probably overkill but I was swooned by it's slew of 7300 V/us.

When I first powered the device I realized my switching supply, that provides the +- 15 rails for the opamps, was more like +-18 (well outside my digipots ability to fix) so I substituted some resistors giving me about +-10Volts for reference going forward.

Some basic tests with the DDS on the AD9102 give me <4ns full scale rise time. For this test the output is 50 Ohm an to a 50 Ohm load at the scope over 50 Ohm coax.. did I say 50 Ohm? The peek to peek voltage of all wave forms is 5.68V and remains flat from 100KHz up to 50MHz so I'm quite pleased with that (about 25dBm constant over the range. I'll improve on that once I nail down the SMP supply voltages.

What is notable from my design is the distinct lack of a user interface. Currently that it being performed by the serial port, I might look at touch screen this and that in the future but it's not the primary focus at this stage. I just want to get a good DAC.

As the only tool I have available is a 100MHz DSO I'm not able to provide any harmonics around the output signal quality and I already know they are not so hot because I have a noisy negative rail that I'm hoping to fix by replacing the suspected damaged components this weekend.. and if that does not fix it I'll be desperately posting for help here


Here is my list of things to do for the second spin of the board and things I'm not sure about.

The MASW-007107 RF Switch is a lot cheaper. I put it on the board
and then noticed insertion loss goes sky high below 2GHz. So I
got scared and just went back to the HMC544A that has a flat loss
to DC. Having said that we really do need exceptional performance at
10MHz???

Do we really need the MCU clock syncronised with the ADCs?
If not then perhaps remove the AD9514 in place of the two
outputs of the LMX2582. The LMX alone has a far better jitter
performance at 47fs RMS @ 1.8GHz. The AD9514 states 225fs jitter.
So I'm probably just making things worse by using it.

Use BGA parts for the CPDL and ATSAM4E to save HEAPS of PCB space.

Actually calculate and have a buffer for power budget. 3.3 Digital is
already exceeding it's 500mA limit and still working.. Amazing.

Put a low pass filter on the DAC outputs.. the wave form will have step noise without it.

Seeing as we have so much spare space and pins on the CPDL perhaps we could replace all the glue logic on the board with that as it's all currently
co-located in or around the same area anyway.

Should have put this first but just to torture those who can not read a full post The schematics are not 100% tested and probably do contain lots of bugs that I have not yet tested. I've plastered a large and hard to ignore note to that effect on the first page of the schematic.

Thanks, that's all for now.

[David Chamberlain]

Here is my most basic startup sequence to get the AD9102 outputting a sine wave from the DDS. This is a key step in validating your master clock input is working and the chips on the board the correct way up.

For reference the data sheet is here

For the clocking three interface examples are given on page 20. LVDS or PECL differential clocks or a single ended CMOS driver. I went with PECL, and anyway the datasheet is not clear on what are considered "low frequencies" where the CMOS version would work, if I had to guess I would say no more then 20MHz? No idea.

My clock is coming from the AD9514 distribution chip. It's has three channels. Out 0 goes to AD9102 Ch0, Out1 to Ch1, and Out2 to the MCU divide by nine. My original idea was to have the MCU clock synchronized to the DAC clocks but think I wont bother with that so much now.  Anyway the AD9102 clock feeds are set as LVPECL 410mV.  The AD9514 is a bit mind bending to configure as it has 11 control lines each with four possible states, I left a non placed zero ohm resister for S1 in case I needed to bump up the LVPECL from 410mV to 790mV but as it's working is not needed.

OK the clock is sorted lets get to the AD9102 registers and the sine wave.

The SPI interface on reset is a standard 4 wire job MSB first R/W flag, 15 address bits and 16 data bits. If you read a few registers you will start to get your first impression of how wrong a datasheet can be with lots of reset values being incorrect including some reserved bits. So for that reason I played it safe and just made it a rule to read / modify / write every register using masks to ensure I did not alter any bits I'm not supposed to.

Not relevant for the sine wave but hands-up who can tell me how many bits long each sample is in SRAM and where in the 16 bit register you should put it. I'll even tell you where to look end of Table 14 page 27. If you answered 12 and 0 then you could not be blamed SRAM_DATA should read top line SRAM_DATA[15:8] and  bottom SRAM_DATA[7:2].

It's clear lots of reserved registers are for the AD9106 four channel version, but not all are.

Onward.

After power up do a hardware reset for fun, take a guess at how long you should hold the reset line low because the datasheet will not tell you.

Ensure pattern generation is not running. For this disable the trigger line and clear RUN (bit 0) in PAT_STATUS (0x001E).

Next configure DACRSET as I'm using the on board RSET resistor - that determines our full scale current at the output - so set DAC_RSET_EN [bit 15] and DAC_RSET = 0 [4:0] in DACRSET [0x000C]. 

In WAV_CONFIG [0x0027] we select our PRESORE_SEL [5:4] = 0x3 for DDS output, and WAVE_SEL [1:0] = 1 for basic Prestored waveform

Set DAC_DIG_GAIN[15:4]=0x400 in DAC_DGAIN[0x0035] this is for a gain of 1. The chip defaults to gain zero so if this is not set nothing will come out.

Next is the two tuning word registers DDS_TW32 [0x003E] for 16 bits MSB and DDS_TW1 [0x003F] for 8 bits LSB that sets the actual desired DDS frequency generated. The actual frequency is given on page 23 as DDS_TW × fCLK/2^24 so depends on your clock. Lets just go for a 180MHz source clock and 5MHz output gives TW32 = 0x0750 TW1 = 0x0075.

That's it all that's left it to run and trigger.
Again in PAT_STATUS set the RUN bit, and then pull the trigger line low and hey presto a 5MHz sine wave.


[EDIT] I neglected to mention an important concept of Shadow Registers, they are meant to allow you to make modifications while the pattern generator is running. From the datasheet.

Most SPI accessible registers are double buffered. An active register set controls operation of the AD9102 during pattern generation. A set of shadow registers stores updated register values. Register updates can be written at any time. When configuration update is complete, the user writes a 1 to the
UPDATE bit in the RAMUPDATE register. The UPDATE bit
arms the register set for transfer from shadow registers to active registers. The AD9102 performs this transfer automatically the
next time the pattern generator is off. This procedure does not
apply to the 4k × 14 SRAM. For the SRAM update procedure, see the SRAM section.

At any rate the example for the sine wave I gave above will work from boot, but changing the tuning words on the fly seems like it can't be done without stopping and starting the pattern generator, although I'm yet to confirm that.  Also the fact that I do not need to perform a ram update to get a basic sine wave at boot tends to contradict the description of how shadow registers work already.

[David Chamberlain]

Attached for convenience are the register definitions for the AD9102. I have been correcting inaccuracies in the data sheet as I go but as it's not fully exercised yet I will update the attachment if and when I find any errors.

The relevant helper functions for the read / modify / write are given below.

Here is an example usage.

Code: [Select]

r = drv_ad9102_open(0, DACRSET);
drv_ad9102_bit_set(DAC_RSET_EN);
drv_ad9102_val_set(DAC_RSET_MSK, DAC_RSET_IDX, 0x0000);
drv_ad9102_close();


Code: [Select]

uint8_t active_channel;
uint16_t active_reg;
uint16_t active_val;

uint16_t drv_ad9102_open(uint8_t channel, uint16_t reg)
{
if(channel==0) {
active_channel = DRV_SPI_AD9102_CH0;
} else {
active_channel = DRV_SPI_AD9102_CH1;
}
active_reg = reg;
active_val = drv_spi_read_single(active_channel, reg);
return active_val;
}

void drv_ad9102_close(void)
{
drv_spi_write_single(active_channel, active_reg, active_val);
active_channel = 0xFF;
active_reg = 0xFFFF;
}

void drv_ad9102_bit_set(uint16_t bitmask)
{
active_val |= bitmask;
}

void drv_ad9102_bit_clr(uint16_t bitmask)
{
active_val &= ~bitmask;
}

uint16_t drv_ad9102_bit_read(uint16_t bitmask)
{
return active_val & bitmask;
}

void drv_ad9102_val_set(uint16_t bitmask, uint8_t idx, uint16_t val)
{
active_val &= ~bitmask; // out with the old.
active_val |= (val << idx) & bitmask; // in with the new.
}

uint16_t drv_ad9102_val_read(uint16_t bitmask, uint8_t idx)
{
return (active_val & bitmask) >> idx;
}

[edit 1] Found an error of my own making. START_ADDR_IDX and STOP_ADDR_IDX were 5 and should be 4. Corrected in rev1 of header attached.

[David Chamberlain]

Square wave from SRAM just two full scale samples. Input frequency is 167776160 Hz, 83.9MHz out. I'm at the limits of my scope bandwidth here with 0.35 / 100MHz rise time so I'll not be able to see if it settles flat on the tops and bottoms like it does at lower frequencies.

First picture is terminated in to 50Ohm.


Second image is unterminated.

[bloguetronica]

Nice board! The sine waves don't seem bad, but the frequency is sure to be on the limit for a 180MSPS DDS, even if you are using Sin(x)/X compensation (I bet you are).

As for datasheet inacuracies, I've had two experiences such as yours, one regarding the AD9854 (corrected on Rev. C, after I opened a case), and another one on the AD9833/AD9834 (opened a case recently, but I'm still waiting for the correction to be made. Anyways, the error was pretty much the same. Where it is:

- SCK idles high between write operations (CPOL = 0)
- Data is valid on the SCK falling edge (CPHA = 1)

It should be:

- SCK idles high between write operations (CPOL = 0)
- Data is valid on the SCK falling edge (CPHA = 1)

Anyway, I don't mean to hijack this post. I'm curious to see the schematic.

Kind regards, Samuel Lourenço

[ogden]

I wonder why your AWG have no low-pass LC filter between DDS and output amp?

[bloguetronica]

I wonder why your AWG have no low-pass LC filter between DDS and output amp?

Good point ogden. By the looks of the PCB, it didn't seem to have any kind of filter after the DDS, but the schematic confirms it.

David, I would recommend you to have a high order Chebyshev filter (Butterworth is better, since the group delay is limited, but you need tighter tolerance components). I would recommend a 0.01dB flat Chebyshev, 5th order, at least. Fc should be set to no more than 1/3rd of your sampling rate.

Kind regards, Samuel Lourenço

[David Chamberlain]

@bloguetronica : That must be an extremely subtle error in the AD9833/AD9834 datasheet, I still can't see it

Your not hijacking the thread at all, in fact it's been dead for some time and I welcome the comments. The schematic was posted at the top of this thread but I've attached a newer revision of the schematics... the only change is a correctly wired Ethernet port 

The other major issue I am yet to fix is the power supply, I did not design enough current in to it to drive both outputs at full tilt so the negative waves were being clipped.

Sin(x)/X perhaps on the scope I can not recall if it was enabled but probably was, it's not a feature of the AD9102.

@ogden and @bloguetronica : I did design a filter to go on the outputs but ditched it before I got the first spin of the board. The main reason for ditching it was I became concerned about the phase relationship between the two channels. if I wanted for instance I wanted 12MHz on one and 4MHz on the other then I presumed I could never get them to cross zero at the same point. Or just an expression of my misunderstanding on the topic. So figured if I built the thing I could play around with the filters later. 

I do need one.. to quote Primer "It's fine. It's fine. Just remember to put it back, okay? Your emissions went up like 300 percent."

[ogden]

if I wanted for instance I wanted 12MHz on one and 4MHz on the other then I presumed I could never get them to cross zero at the same point.

For 2 channel generator you shall have phase control for each channel anyway. This will allow you to tune phase as you wish or even do phase error calibration/correction. 4 and 12MHz is far enough from filter cutoff frequency which supposedly is slightly above 50MHz, thus phase error at given frequencies could be not that bad as you think, especially if you use quality components. Anyway it is good idea to run montecarlo simulation for flter in question and see - expected phase error spread is acceptable for you or not.

So figured if I built the thing I could play around with the filters later. 

You definitely want to place filter *before* amplifier, so "add filters later" means more or less new board

[bloguetronica]

David,

Expect a lot of waste bandwidth, and not just because of the filter. I though that the AD9102 that Sin(x)/x envelope compensation, sometimes called sinc compensation. If it hasn't, expect a roll-off due the implicit Sin(x)/x envelope of the DAC, which will affect the higher frequencies. Of course this is not to be confused with the Sin(x)/x interpolation of the oscilloscope, which is a different subject.

For instance, for a 80MSMS function generator I've designed, that had a 23MHz 5th order 0.01dB Chebyshev filter in it, I've got a 8MHz sine with a 0.1dB attenuation. Thus, in your project, expect to have 16MHz maximum with acceptable attenuation, and that is for sine waves. For more complex waves, you'll have the higher harmonics suppressed by the filter, or at least affected by the DAC Sin(x)/x envelope.

As for the filter, it is better for you to implement a 50\$\Omega\$ matched filter. If the AD9102 DAC only accepts 200\$\Omega\$, you'll have to put a buffer between the AD9102 DAC and filter. You can also design a 200\$\Omega\$ matched filter, but for the kind of frequencies you want, the capacitances are small and parasitics may be a very significant factor. Doing your final amplification/buffering after the filter is a must.

Kind regards, Samuel Lourenço

[David Chamberlain]

Hi, I redesigned the front end by basically following the example in the THS3091 spec sheet. I noticed this is the same topology used in some Siglent Arb as done by Dave


I included the recommended 60MHz 5th order Chebyshev LPF. It gives -40dB @ 170MHz (the DAC clock) I don't know what I was expecting but perhaps a sharper roll off OR does this look about typical? I'll try increasing the order.

Note this filter is 250Ohms. If I change it to 50Ohms (40.12464pF, 173.07nH, 83.67864p,  173.07nH, 40.12464pF) I get identical Frequency response to the one below.

And these are not cheap, my opamp budget just increased to AU$38 per channel!!!!

[duak]

Arbitrary Waveform Generators usually have Bessell type reconstruction filters to preserve the phase relationships between the higher order harmonics.  If they aren't, the ultimate shape of the waveform will be affected especially near faster transitions.  Unfortunately, it takes a higher order Bessell filter to do the job of the Chebyshev.

Outside of the transition region around the corner frequency all low pass filters are the same: 20 dB per decade ultimate rolloff per filter order.  This appears to be a 5th order filter so it'll be 100 dB down at 10X its corner frequency.  By diddling with locations of the various poles and zeroes the transition characteristics can be changed.  Compare the frequency response of this filter with a 5th order Bessell and you should see what I mean.   Note also that the Chebyshev has some amplitude ripple around the corner frequency.  BTW, a Chebyshev filter with 0 amplitude ripple is a Butterworth.

If you are able to design and build a filter with arbitrary input and output impedances, there can be an advantage in having a low input impedance, say 100 ohms, and a higher output impedance, say 1000 ohms, there will be less voltage loss thru the filter within the passband. ie., if both input and output impedances were 100 ohms, the output voltage would at best be half that of the input.

Hope this makes sense,

Best o' luck

[imidis]

Hi, just want to add some encouragement. I was just thinking I wonder if anyone has thought of taking this on. It seems doable, but a bit of effort! Don't give up!

[David Chamberlain]

Unfortunately, it takes a higher order Bessell filter to do the job of the Chebyshev.

No kidding, I just did a quick test to show this. But I'm not seeing a drastic improvement in the phase between the two.

Thanks for the idea about increasing the output impedance I will give that a try also.
 
For any one interested the simulator is TI's TINA I would prefer to be using LT Spice but the opamp models are only available for TINA. The filter calculator is AADE - http://w1hue.org/filter.html




Green trace is the Chebyshev

[duak]

David, try doing a time domain simulation by putting in various input waveforms such as pulse, square, triangle and ramp to see how the filters respond.

Cheers,

[David Chamberlain]

David, try doing a time domain simulation by putting in various input waveforms such as pulse, square, triangle and ramp to see how the filters respond.

Cheers,

Thanks duak, I think I see it now.

Square wave with 1ns edges [VAC], otherwise same filter schematic as my last post.

[xaxaxa]

Square wave with 1ns edges [VAC], otherwise same filter schematic as my last post.

That overshoot is more a consequence of the filter being sharper than due to the phase of the filter; in other words the chebyshev filter is "working as intended" - an ideal brick wall linear phase filter would produce that overshoot as well, since you can think of an ideal LPF as convolving the input signal with a sinc function.

[duak]

Yep, as David's time domain responses show, the Bessel filter is still not perfect.  The Gaussian filter apparently eliminates all overshoot but I've never designed one and don't know how easy it would be to realize for this application.  On the other hand, elliptic filters incorporating zeroes can give some additional attenuation at some frequencies while sacrificing attenuation at others.  This sort of happens anyway because the L's and C's aren't perfect and have self resonances.

If memory serves the Stanford Research DS345 30 MHz synthesizer has two types of reconstruction filters.  One for sine and one for arbitrary - I suppose each is tuned to give the best response for the waveform.  Since the amplitude of the waveform is controllable it could be adjusted in sine mode to compensate for any passband amplitude ripple.

I remember using one in 1990 or so and was quite impressed at how much it could do and how well it worked for its price and size.  I looked into building one but didn't get past the understanding how it works phase.

[bloguetronica]

Hi,

Forgot to mention. If you are doing an arbitrary function generator, or if you expect to produce some steep signals (square waves, step ramps, etc), you are better of with an high order Bessel filter (say, 7th order or even 9th order). I think I've mislead you with my example, because my function generator only produces sine and triangle waves. Actually, the images attached shows the step response I get when forcing it to produce a square wave (by setting the AD9834 frequency to zero and by changing the phase between 90 and 270 degrees). Mind that this is a 0.01bB Chebyshev aligned filter (the closest to Butterworth), so it could be worse.

Thus, any other filter except Bessel will produce an overshooting step response. Elliptic filters are even worse, Butterworth filters are simply not worth it, as you'll probably end up with a Chebyshev filter (kind of) if you use practical values. So, you could do a Bessel 9th order filter. Mind that the roll-off starts very early with this kind of filter, so an high order is a must.

Kind regards, Samuel Lourenço

[bloguetronica]

I've done a quick simulation, and I've seen that the Bessel is a disgrace. Not only it starts to roll-off very early, but the attenuation is very poor. I think the best compromise is a 7th, or better, a 9th order Butterworth filter.

I should remark that the 5th order Chebyshev filter that I used was a bit lacking, but it was the one possible due to the lack of space on the PCB. Ideally, it should be a 7th order Chebyshev (0.01dB).

See the results here:
http://www.wa4dsy.net/cgi-bin/lc_filter3?FilterResponse=Lowpass&poles=9&cutoff=60&funits=MHZ&Z=50

Kind regards, Samuel Lourenço

[bloguetronica]

Hi,

Did a simulation of two potential filters that you might be interested in. I'm using one of these on my AD9102 based AWG (in phase of prospection). The first one is 7th order Chebyshev aligned filter (0.01dB), that has the cutoff frequency defined to approx. 53MHz (the cutoff frequency of this kind of filters corresponds to the ripple amplitude, this it is considered to be -0.01dB and not -3dB). The second is a Butterworth aligned filter, with its cutoff frequency set to 55MHz (I'm choosing this one).

See the results of the partsim simulation attached. I still didn't dared to simulate a Bessel aligned filter, but I guess it would be interesting too.

Kind regards, Samuel Lourenço

[bloguetronica]

Hi,

Simulated a Bessel filter with a 55MHz cut-off. The results are quite horrible. You can see the PDF attached (ignore the Butterworth part, since the values were changed to meet Bessel filter specs as per this link: http://www.wa4dsy.net/cgi-bin/lc_filter3?FilterResponse=Lowpass&poles=9&cutoff=55&funits=MHZ&Z=50).

You can use it as well as any other filter, but mind that the the attenuation at 16MHz is significant. This is even worse that the DAC envelope.

Kind regards, Samuel Lourenço

[David Chamberlain]

@bloguetronica, thanks for the effort, simulations and ideas. I'll get a chance to look more closely over the weekend.

So you've also done a AD9102 AWG? I would be very keen to get any feedback from you on the chip itself. Despite the higher sample rate it's quite a different and perhaps less versatile chip than the AD9834.

[bloguetronica]

Hi David,

I've done one based on the AD9834, but I'm yet to do one based on the AD9102. However, the datasheet of the last raises many questions. For example, having a 200 resistor, what would be the minimum and maximum voltages to be expected on the waveform. I'm looking for a module on eBay, but found none yet.

Kind regards, Samuel Lourenço

[Tueftler]

Hi all,

I am jumping into this interesting thread. Before losing myself in the complexity and pitfalls of the AD9102 / AD9106, I would be very grateful if you could share your experience with me and estimate if it is possible to generate an amplitude modulated signal for the following purpose?

For a multi-channel detection system with digital lock-in realization, I need a programmable sine wave amplitude modulation for a programmable sine wave carrier signal with the following ranges:
f_m = 1 kHz ... 1 MHz
f_c = 200 kHz ... 10 MHz

Does this chip really save time and complexity over a standard high-speed DAC?

In general, I see the following 3 possible solutions (with 1+2 being fully on-board solutions):

  1) AD9102 / AD9106 (for amplitude modulated signal?) + single-ended buffer + low pass filter + VGA (for programmable amplitude: 10 mV ... 1 V) + bias tee (for DC component) + buffer
  2) AD9707 (DAC, 175 MSPS, 14 parallel bits) + single-ended buffer + low pass filter + buffer
  3) Dual channel laboratory waveform generator (Agilent or HP or...) + coaxial frequency mixer with coaxial output to board + on-board bias tee (for DC component) + buffer ... + sync from waveform generator to the on-board FPGA (for the digital lock-in mixing)

I see the following points:
 1) Pro: Few FPGA I/Os needed. Contra: A lot of additional components needed, elaborative programming
 2) Pro: Fewer components needed? DC + amplitude modulated carrier frequency can be directly programmed? Contra: Maybe jitter problems, maybe stressing the FPGA bandwidth, a lot of I/Os needed
 3) Pro: Pure sine waves, fast design, only one I/O needed for synchronization. Contra: No on-board solution, synchronization with wave generator maybe not ideal for the digital lock-in mixing on the FPGA

For which solution would you vote for?