30 MHZ ad9850 DDS Signal Generator in 12$

[paulie]

Now it happens that some of these cheap modules apparently were fitted with this wrong 75MHz filter (see http://www.pongrance.com/DDS-9850.html).

I'm convinced this was not a mistake. Chinese hobbyists, being considerably smarter than their average western counterpart, enjoy overclocking these parts which means considerable improvement in upper end performance.

75MHz LPF the chip maker recommends for the AD9851 running at 180MHz.

IIRC OP has mentioned clocking his beyond to 300mhz which might be pushing it but would benefit from even higher cutoff. Personally I have one of the new "corrected" units but would very much like to get the old "defective" ones. Guess I'll have to take matters into my own hands and start dicking with those SMD caps and inductors.

[Mechatrommer]

*See also http://en.wikipedia.org/wiki/Zero-order_hold and how the frequency response will have a 3.9224 dB roll-off at Nyquist frequency (Half the sampling frequency).

assuming one have done this a perfect 0_order_hold for 125MSps on that 9850 output, perfectly tuned for 30MHz signal output. then slap the 9850 to output the 164KHz (1Msps) now what? the T has changed from 8ns to 2us... i guess one have filtered the 8ns out but still leaving 2us - 8ns = 1.992us stairstep visible.

[Kalvin]

*See also http://en.wikipedia.org/wiki/Zero-order_hold and how the frequency response will have a 3.9224 dB roll-off at Nyquist frequency (Half the sampling frequency).

assuming one have done this a perfect 0_order_hold for 125MSps on that 9850 output, perfectly tuned for 30MHz signal output. then slap the 9850 to output the 164KHz (1Msps) now what? the T has changed from 8ns to 2us... i guess one have filtered the 8ns out but still leaving 2us - 8ns = 1.992us stairstep visible.

No. The samples are always output at constant rate of 125MHz (8ns): When the output frequency is 30MHz, the 9850's DAC will output a new sample at every 8ns.  Even if the output frequency is set to 164kHz, the DAC will spit out new sample at every 8ns. The quality of the output signal (how well the output signal matches to the original sampled sine wave) is dependent of how many bits the DAC has. This is particularily obvious at the lower frequencies: For example, if a DAC has only 4 bits (16 output levels), the output cannot represent the original sine wave as well as a DAC with 10 bit output (1024 levels).

[Kedar264]

you all have detail understanding about dds and all about filtering stuff,can you help me by suggesting output circuit to get precise output 

[Mechatrommer]

No. The samples are always output at constant rate of 125MHz (8ns): When the output frequency is 30MHz, the 9850's DAC will output a new sample at every 8ns.  Even if the output frequency is set to 164kHz, the DAC will spit out new sample at every 8ns. The quality of the output signal (how well the output signal matches to the original sampled sine wave) is dependent of how many bits the DAC has. This is particularily obvious at the lower frequencies: For example, if a DAC has only 4 bits (16 output levels), the output cannot represent the original sine wave as well as a DAC with 10 bit output (1024 levels).

here we go again someone read from theory you missed all the fun.

[Kalvin]

No. The samples are always output at constant rate of 125MHz (8ns): When the output frequency is 30MHz, the 9850's DAC will output a new sample at every 8ns.  Even if the output frequency is set to 164kHz, the DAC will spit out new sample at every 8ns. The quality of the output signal (how well the output signal matches to the original sampled sine wave) is dependent of how many bits the DAC has. This is particularily obvious at the lower frequencies: For example, if a DAC has only 4 bits (16 output levels), the output cannot represent the original sine wave as well as a DAC with 10 bit output (1024 levels).

here we go again someone read from theory you missed all the fun.

Oh no, it is not theory. It it obvious even without theory

[hamster_nz]

*See also http://en.wikipedia.org/wiki/Zero-order_hold and how the frequency response will have a 3.9224 dB roll-off at Nyquist frequency (Half the sampling frequency).

assuming one have done this a perfect 0_order_hold for 125MSps on that 9850 output, perfectly tuned for 30MHz signal output. then slap the 9850 to output the 164KHz (1Msps) now what? the T has changed from 8ns to 2us... i guess one have filtered the 8ns out but still leaving 2us - 8ns = 1.992us stairstep visible.

Those screen grabs were just an example of a different DAC output, running at approximately 100th the speed of the DDS chip. Sure,if you put the 30MHz filter on my chip it wouldn't help much, but on the DDS chip it will give a clean signal.

[hamster_nz]

you all have detail understanding about dds and all about filtering stuff,can you help me by suggesting output circuit to get precise output 

This has a design for a completely passive 30Mhz reconstruction filter: http://www.ti.com/lit/an/slaa135/slaa135.pdf and this is an active one: http://pdfserv.maximintegrated.com/en/an/AN3520.pdf.

Due to the sample frequency you should really be using a 62.5MHz reconstruction filter, so you might want to adjust things a bit and check the bandwidth of the parts. Another promising looking part is https://www.hittite.com/content/documents/data_sheet/hmc900lp5.pdf.

But if it was me doing things just for fun, I would look for a dual video op-amp with chip about 60MHz gain/product bandwidth (something like a ADA4898-2), and chain them both when configured for 1x gain. It won't be perfect, but it should be relatively inexpensive and work reasonably OK. It would also be quite fun to experiment with.

[Kleinstein]

The required reconstruction filter of the DDS only depends on the sampling frequency, not the frequency of the output signal. So for 125 MHz sampling the edge can stay a something like 40-50 MHz, depending on how steep it is. This filter will still work smoothing the smaller steps of a 1 MHz sine wave, as the timing is the same. The 62.5 MHz is the frequency where the filter should provide sufficient damping. So half the sampling frequency is the theoretical limit. The practical limit is more like 1/3 of the sampling frequency - so 40 MHz in this case. Even then some adjustment of the amplitude may be helpful. The closer one gets to the the theoretical limit, the better the filter needs to be. If one needs more - choose a faster chip (e.g. AD8951).

In this frequency range the passive Chauer filter is the typical solution - its rather simple and low part count. This type of filter is already on the module. After that some amplification is helpful - for more power and also to isolate the filter from the output impedance. I don't see much advantage in using 2 rather slow OPs - a single higher speed OP (in the 60-300 MHz GBW range) is likely the better choice. Something like 2 OPs in parallel might be needed to get higher power. Finally an attenuator may come handy.

[Mechatrommer]

*See also http://en.wikipedia.org/wiki/Zero-order_hold and how the frequency response will have a 3.9224 dB roll-off at Nyquist frequency (Half the sampling frequency).

assuming one have done this a perfect 0_order_hold for 125MSps on that 9850 output, perfectly tuned for 30MHz signal output. then slap the 9850 to output the 164KHz (1Msps) now what? the T has changed from 8ns to 2us... i guess one have filtered the 8ns out but still leaving 2us - 8ns = 1.992us stairstep visible.

Those screen grabs were just an example of a different DAC output, running at approximately 100th the speed of the DDS chip. Sure,if you put the 30MHz filter on my chip it wouldn't help much, but on the DDS chip it will give a clean signal.

right! this cost me dismantling my whole unit again and probing job. so yeah, this bastard will output at fixed 125MHz or whatever clock you put it in, no prescale or whatever everything is just a simple freq/tuning formula exactly as in datasheet must be few things to happen for a disaster 1) my everlasting memory with AWG DDS mechanism, 2) you put a picture with as little description on it. indeed its 1.3MHz as the "input clock" i cant imagine why someone want to do that? with 5Hz requirement as you stated i believe one still can get with the recommended clock, 0.029Hz step, wait a second... (checking the ad5541 datasheet) its a DAC! not DDS! 3) today must be a bad day for me. what a waste of the whole night someone must be cleaning this thread up...

hence to the OP, you asked what filter? none, because your board already have one on the sina output, that elliptic low pass, otherwise you need to tap sinb and do whatever suggested here for T = 8ns :|

[hamster_nz]

right! this cost me dismantling my whole unit again and probing job. so yeah, this bastard will output at fixed 125MHz or whatever clock you put it in, no prescale or whatever everything is just a simple freq/tuning formula exactly as in datasheet must be few things to happen for a disaster 1) my everlasting memory with AWG DDS mechanism, 2) you put a picture with as little description on it. indeed its 1.3MHz as the "input clock" i cant imagine why someone want to do that? with 5Hz requirement as you stated i believe one still can get with the recommended clock, 0.029Hz step, wait a second... (checking the ad5541 datasheet) its a DAC! not DDS! 3) today must be a bad day for me. what a waste of the whole night someone must be cleaning this thread up...

hence to the OP, you asked what filter? none, because your board already have one on the sina output, that elliptic low pass, otherwise you need to tap sinb and do whatever suggested here for T = 8ns :|

Sorry about that - I thought I was being pretty explicit when I said "Oh, and as an illustration,  here is what the output of a DAC looks like without a reconstruction filter" in the post with the screen grabs.

[Tac Eht Xilef]

you all have detail understanding about dds and all about filtering stuff,can you help me by suggesting output circuit to get precise output 

Sorry OP, it's turned into one of those threads ... 

It's been a while since I looked or thought about it, but I don't think you're going to find a a drop-in example for you to copy. In reality, it's not that easy to solve in a way that makes it worthwhile (e.g. low distortion, stable & flat from near DC->15/20/30MHz, etc) at the price / performance required. There's several reasons cheap DDS-based signal generators tend to top out at 2/5/10 MHz - and that's one of them.

If you Google around, you'll stumble across the circuit shown in this thread - it was originally designed by PA3CKR for his DDS signal generator project, and IIRC is pretty much pieced together straight from TI appnotes. Supposedly it's good for 40MHz, but at those frequencies you're in an area where layout & construction matters just as much as choice of device - it's not a job for an amateur unless they plan on learning a lot.

Personally I'd look at something like the Analog Devices AD600 / AD602 for the basis of the AGC stage - from memory, the datasheet of one or the other has a nice-looking 2-stage AGC example that should be suitable. From there, I'd be looking at high-frequency line driver amps from the likes of TI as an output stage.

[Mechatrommer]

Sorry about that - I thought I was being pretty explicit when I said "Oh, and as an illustration,  here is what the output of a DAC looks like without a reconstruction filter" in the post with the screen grabs.

the output of DDS is a DAC, and sometime in other system, "sampling clock" <> "input" or "base" frequency.

[niekvs]

you all have detail understanding about dds and all about filtering stuff,can you help me by suggesting output circuit to get precise output 

Please also see page 17 of the datasheet, which shows an implementation of a 42MHz low pass filter (the LC filter on the right). ( http://www.mpja.com/download/ad9850.pdf )

The required reconstruction filter of the DDS only depends on the sampling frequency, not the frequency of the output signal.

This is true, if you just make sure to stay under the Nyquist limit (half the sampling freq). However, the location of the "images" does depend on the output frequency (they are located at Freference (125MHz) - Foutput. See also page 9 of the datasheet, so if for example you know you will only use this thing for lower frequency outputs, you can relax the requirements of your filter a bit.

Anyway - glad most here now seem to understand and agree that, while counterintuitive, you don't need to output all those values so that when you connect those dots directly make a pretty sine wave on paper.  Statements like "you will not and cannot possibly use all 10 bits in each 360 degrees of an output sine wave once you get above certain frequencies" are therefore more or less irrelevant. It's indeed "simple math", though not as simple or as intuitive as it may seem at first sight... It's quite magical in fact, when you first "get it", and therefore a pretty interesting subject!

[Kalvin]

Hi all,

I created a simple DDS simulator for LTSpice. The user can vary different DDS parameters like DDS clock, output frequency and number of bits used for DAC and observe how these parameters affect the filtered DDS output signal purity.

When the DDS parameters are set as follows:

- DDS clock frequency = 125.0 MHz.
- DDS output frequency = 30.1 MHz.
- DAC resolution = 10 bits.
- Lookup-table size = 2**12

The result is quite clean sine wave with almost -60dB noise level (see figures a).

When the DDS parameters are set as follows:

- DDS clock frequency = 125.0 MHz.
- DDS output frequency = 30.1 MHz.
- DAC resolution = 4 bits.
- Lookup-table size = 2**8

The result is contains some noise already at -35dB (see figures b).

Pls find the files in the attached zip-file "dds-with-ltspice.zip" (See the last file in the attachments). The Python script "dds.py" will generate DDS DAC output signal which will be imported into simulation file "dds-with-python.asc" containing a 64MHz reconstruction filter.  The program was tested using LTSpice and Python 2.7 running in Linux Mint.

Have fun!

Br, Kalvin

[Kalvin]

Here is the same simulation with the output frequency set to 3.01MHz.

The "c" files was generated with the following parameters:

DDS clock frequency = 125.0 MHz.
DDS output frequency = 3.01 MHz.
DAC resolution = 10 bits.
Lookup-table size = 2**12

The resulting sine-wave has -55dB noise level.

The "d" files was generated with the following parameters:

DDS clock frequency = 125.0 MHz.
DDS output frequency = 3.01 MHz.
DAC resolution = 4 bits.
Lookup-table size = 2**12

The resulting sine-wave has close to -40dB noise level.

[niekvs]

A nice set of tests!

On a related note, here's a excellent document explaining and quantifying the noise resulting from the limited number of bits in the DAC as well as the effect of the truncation of the phase accumulator (in case of the AD9850, the DAC is 10 bits, and the number of bits of phase after truncation is 14). See chapter 4 for the relevant information.

http://www.ieee.li/pdf/essay/dds.pdf

Generally, with the specs of the AD9850, most people probably won't have to worry about these details and should know that it works very well (unless you're not filtering correctly.. And that, if you're getting triangle waves at 30MHz, you're doing something wrong.

[Kalvin]

A nice set of tests!

Thanks! I just wanted to play with LTSpice, do real mixed-signal analysis so that an external program (Python script in this case, see my posting above with an attachment "dds-with-ltspice.zip") creates a file containing a signal to be imported into LTSpice simulation, and the generated signal be used as a stimulus (input to the reconstrcution filter). It was easier than I though. More info about these PWL-files can be found here:
http://www.linear.com/solutions/1815

[paulie]

An Precession Signal generator is very easy and affordable make using an arduino and dds synthesizer (ad9850) .

True. Only took me  few minutes to make use of the Ebay module gathering dust thanks to your excellent instructions. I am really impressed by the rotary encoder method for setting frequency. AD8951 has been ordered so I can use my recent 40mhz GPSDO circuit as input clock for ultra-precise and stable DDS generator. Too bad AD8950 don't have similar input clock ability. Thanks for a great thread.

[vinicius.jlantunes]

Subscribed.

[bingo600]

AD8951 has been ordered so I can use my recent 40mhz GPSDO circuit as input clock for ultra-precise and stable DDS generator.

@paulie

A 40 milli-Hz input would mean quite a different LP filter , even if the 51' can up the clock 6*  to 240mHz 

/Bingo

[miguelvp]

Wonder what happened to paulie, not active since May 30 so unlikely to see your post

[AustinTxBob]

Looks like a fun way to play with the AD9850.  I hooked mine up and it seems ok running at the default 10MHz.  My goal with this is an antenna analyzer for HF frequencies.

[AustinTxBob]

The schematic and the code have a difference.  The schematic lists fqup going to 10 and rest going to 11 but the code has them reversed.

Pretty unusable at higher frequencies as predicted.  Seems like it will work up to 15MHz for my purpose though.

[Chatchai]

The AD9850 good for me  .