30 MHZ ad9850 DDS Signal Generator in 12$

[hamster_nz]

I know what you mean but in DDS literature Aliases mean frequency components Fclock plus minus Fout. They can be filtered out and they even can be filtered in (so to speak) or selected to become the DDS signal gen output. This is described in practically any Analog Devices DDS datasheet. Try opening AD9850 datasheet for example and search for all instances of "alias", see what you can learn.

I just did read the datasheet - (alias appears only 6 times, all on page 9 ) - and I did learn one thing. It must be a local AD terminology thing (or maybe USA vs "the world" thing) - as they refer to adding "alias filters" on DAC, which removes any undesirable out-of band signals on the ADC output.  They definitely DO NOT not have an anti-alias filter on the DAC output.

Where I'm from these DAC output filters are usually referred to as "reconstruction filters" (which can actually do a little more than an alias filter) or ""anti-imaging filters".

Shrug, must be a geographic/cultural thing.

[Kedar264]

I almost forgot to mention ad9850 has 4 outputs 2 sine waves 90°phase shifted and 2 square waves .

[Mechatrommer]

Say you want a 62.5Mhz sine wave output.  Well, it ain't gonna happen.  125Mhz / 62.5Mhz = 2 steps, high and low.  1 bit sine wave = square wave.  Filter that...
Want a 31.25 sine wave output?  Ain't gonna happen again. 125Mhz / 31.25Mhz = 4 steps, high, 1/2 high, 1/2 low, and low.  2 bit sine wave?  No...

Maybe you should go over your DSP/filtering basics. "Filter that", well that's why I was referring you to page 9 (and 8 ) of the datasheet: it will show you how to do it.
And this whole thing about 4 bits of DAC resolution still makes no sense. The part has a 10 bits DAC. It's not "2 steps, high and low", but 2^10 (1024) possible values. They will vary in phase, and so vary in amplitude, as the frequency won't be an exact multiple.

the fact is, this thing is not a basic DSP thing. 125MHz clock is the max it can get to, the 10bit DAC is the max it can get to, but only at some  golden freq setting. at other freq, it will prescale the clock, use lesser bits etc through its definite DDS wisdom... at 62.5MHz, it cant use all 10bit dac because that way it will need around 64GHz of clocking 1023 data. at nyquist freq, it only can clock 2 points, hence 1 bit DAC usable.

take our fellow friend example...

if you look closely, it aint 125MHz clocking there, its 1MHz albeit it only generating 164KHz of signal, and only 2 bits (4 values) usable. so that proved there is a "definite wisdom" going on in the DDS., not the  basic DSP stuffs.

[miguelvp]

I don't think hamster was using the ad9850 he just mentioned a DAC and probably controlling the steps, most likely the DAC he was using could handle more resolution, but he was trying to make a point.

One thing about the ad9850 is that it will show those steps but not in a controlled way, meaning that the high frequency noise won't be distributed as nicely as in that example, so after applying filters not all the waves would be identical since the high frequency noise would be distributed over all the waves at different points.

But I think it's fine for up to 20MHz which is plenty, otherwise AD do offer other higher spec'd solutions.

[c4757p]

"definite wisdom"

 

[Mechatrommer]

maybe now you can start charting all the bits,clk,freq configuration just like hamster did, and tell us what exactly the formulation on how the DDS can output all the freq range, we have made observation on other DDS sometime ago. you tell us the formula and we can figure out what the "definite wisdom" is.

[hamster_nz]

I don't think hamster was using the ad9850 he just mentioned a DAC and probably controlling the steps, most likely the DAC he was using could handle more resolution, but he was trying to make a point.

- just there for illustration of an unfiltered DAC output.

It's actually a AD5541A , a 16-bit DAC, running an output sample frequency of 1,315,789 HZ. It is being driven by a lookup table of 1024 18-bit entries, with 8 bits of interpolation between entries (giving at worst +/- 1 LSB from a 2^18 entry lookup table feeding the 16-bit DAC). So it is close to perfect.  For that picture the generated frequency was 1/8th the sample frequency, so only 8 different values are being used.

The odd sample frequency has been chosen so I can generate frequencies in about 5 Hz steps (+/- 0.5%) for testing something I'm working on.

[Mechatrommer]

I don't think hamster was using the ad9850 he just mentioned a DAC and probably controlling the steps, most likely the DAC he was using could handle more resolution, but he was trying to make a point.

- just there for illustration of an unfiltered DAC output.
It's actually a AD5541A , a 16-bit DAC, running an output sample frequency of 1,315,789 HZ. It is being driven by a lookup table of 1024 18-bit entries, with 8 bits of interpolation between entries (giving at worst +/- 1 LSB from a 2^18 entry lookup table feeding the 16-bit DAC). So it is close to perfect.  For that picture the generated frequency was 1/8th the sample frequency, so only 8 different values are being used.
The odd sample frequency has been chosen so I can generate frequencies in about 5 Hz steps (+/- 0.5%) for testing something I'm working on.

the point that doesnt clear is that DDS wont use all 1024 lookup table, wont clock at max xtal clock everytime, as some might think just by looking at the datasheet...

[miguelvp]

It's actually a AD5541A , a 16-bit DAC, running an output sample frequency of 1,315,789 HZ.
...

damn I was going to say this:

Mearused: 1312500 (21 pulses in 16us) but I noticed it was doing 8 samples per wave so, 164.5K *8 = 1316000
Middle ground: 1314250

So I guessed 1315000 Hz and had it on my Notepad++ but thought it would be silly to share

[c4757p]

It's not going to change the clock frequency, Mecha. I feel like you have no idea what you're talking about.

[miguelvp]

I lost what I computed but tuned at 30MHz with a 125MHz clock every 25 wave will look alike, with different distortions on the other 24 waves with some being affected badly in amplitude because of the aliasing between the 125MHz clock and the lookup table to get the 30MHz signal, but I didn't examine the datasheet in detail.

[Skimask]

AD9850 always uses the 125Mhz MCLK (or whatever Mhz is going in there) as the source for the accumulator.  No random division going on, just straight up 125Mhz (again, or whatever a person is using for the MCLK).
125Mhz input, 32-bit "tuning word", which is the value that is added to the 32 bit accumulator, the upper 10 bits of which are fed to a sine wave loop up table, which in turn feeds the 10 bit output DAC.

Start off with zero's in everything...
You've got this 'tuning word', which is the adder, set it to a value of "1", just 1, not 0x01, just 1.
MCLK pulse comes in, add the value of the tuning word to the accumulator, accumulator = 1, nothing in the upper 10 bits yet (won't be for another 4MiB pulses)
Keep adding MCLK pulses at the rate of 125 million per second and this 32 bit accumulator will overflow in 34.359738368 seconds (125Mhz / 32bits), giving you an output frequency of 0.02910383045673370361328125 Hz.

Change the tuning word to 2,147,483,648 (2^31), the upper bit of the accumulator flips every MCLK pulse (it's an add, not a multiply, not a look up, just an add), the accumulator overflows, the overflow is thrown away.  But, the upper bit, 31, is also the upper bit of the 10 bit DAC.  Therefore, only 1 bit of the DAC is being used, the MSB.  Therefore, the output value only flips between 2 possible values, high and low.

Change the tuning word to 1,073,741,824 (2^30), the upper 2 bits of the accumulator change on every MCLK pulse.  The upper 2 bits, 30-31, also the upper 2 bits of the DAC.  Only 2 bits of the DAC is being used.  The output value only flips between 4 possible values.

So on down the line...

If the tuning word is less than 2^22 (total accumulator size - upper 10 bits, which again are the 10 bits of the output DAC), then and only then can you possibly get all 1024 values output in the DAC.  And with an MCLK of 125Mhz, that will only happen when a desired frequency of less than 122,070.3125Hz has been selected.  Any higher than that, all POSSIBLE values in the DAC won't get hit each and every time thru the sequence.  They might get hit eventually, but not on each cycle of the outputted sine wave.

What miguelvp said in the last post about being tuned to 30Mhz with a 125Mhz MCLK and every 25th wave being identical sounds about right, although I think it'll actually be every 6th wave will have identical characteristics...the other 5 waves will be fundamentally 30Mhz but with different distortions, harmonics, etc.

[miguelvp]

But I did notice one thing:

the output frequency can be digitally changed (asynchronously) at a rate of up to 23 million new frequencies per second

and

The device also provides five bits of digitally controlled phase modulation, which enables phase shifting of its output in increments of 180°, 90°, 45°, 22.5°, 11.25°, and any combination thereof

Surely that can help if the program driving the AD9850 takes advantage of that to compensate somehow, but I doubt that is used and not sure of the update rate for the phase shifting.

[Mechatrommer]

It's not going to change the clock frequency, Mecha. I feel like you have no idea what you're talking about.

so what is it that you know what you are talking about? that you involved in the design that you didnt tell us? its either clock at 125MHz and keep the same table value for 125 clock count, or prescale the clock. either way, its not going to use different 1023 values throughout a period just as the picture says. thats my best guess, so what exactly it is? it will be usefull if you can shed the light, otherwise, i am right.

[hamster_nz]

I lost what I started but tund at 30MHz  a 125MHz clock every 25 wave will look alike, with different distortions on the other 24 waves with some being affected badly in amplitude because of the aliasing between the 125MHz clock and thet lookup table to get the 30MHz signal, but I didn't examine the datasheet in detail.

If I gave you a repeating series of repeating numbers 0,  1, 0. -1 and asked you what signal those samples represent, what would you say?

If I then gave you this repeating series 0.707, 0.707, -0.707, -0.707 and asked the same question, what would you say that was?

In both cases you would be right, but I could produce another signal that would sample giving exactly the same values..  Without additional information you don't have enough to uniquely identify and be able to reproduce the original signal.

However if I also add that the signal contains no frequency components over half the sample rate, then both series uniquely describe the same wave (a sine wave of the same amplitude) - there is no waveform other than a sine at a quarter the sample rate that will give you those numbers. (Of course with the difference is in the phase).

Likewise, just because the 30MHz generated signal looks different during different cycles it is only because you have not yet put it through a proper reconstruction filter. block everything over 62.5MHz and it will look like a clean sine of constant amplitude - because it is a clean sine, with added noise (i.e. unwanted signal) that is outside of the 0 to 0.5 times the sample rate can be filtered off and discarded.

Assuming you are using a simple DAC (not a one-bit or oversampling one) doesn't matter how many samples you use per cycle of the output signal, as long as you play back more that two and have the correct reconstruction filter then the information is all in there to recreate a signal that faithfully represents the original to the limits of the DAC's resolution.

Of course sometimes getting the correct filter is hard (stop band being steep enough, ripple etc) so the best answer might be to properly double the sample rate in the digital domain, and use a faster DAC. 

[tggzzz]

If the tuning word is less than 2^22 (total accumulator size - upper 10 bits, which again are the 10 bits of the output DAC), then and only then can you possibly get all 1024 values output in the DAC.  And with an MCLK of 125Mhz, that will only happen when a desired frequency of less than 122,070.3125Hz has been selected.  Any higher than that, all POSSIBLE values in the DAC won't get hit each and every time thru the sequence. 

 The reconstruction filter will remove the higher frequencies, leaving only the sine wave below the cutoff frequency. The extent of the HF attenuation will, of course, be determined precisely by the reconstruction filter's "shape".

They might get hit eventually, but not on each cycle of the outputted sine wave.

Correct. So what? It isn't necessary for a value to be output on every cycle of a sine wave.

What miguelvp said in the last post about being tuned to 30Mhz with a 125Mhz MCLK and every 25th wave being identical sounds about right, although I think it'll actually be every 6th wave will have identical characteristics...the other 5 waves will be fundamentally 30Mhz but with different distortions, harmonics, etc.

True only if there is no reconstruction filter.

I get the feeling maths isn't your strong point, and that you don't understand fundamental sampling theory and fourier series. That's nothing to be ashamed of, but you might like to be aware of your limitations.

[niekvs]

If the tuning word is less than 2^22 (total accumulator size - upper 10 bits, which again are the 10 bits of the output DAC), then and only then can you possibly get all 1024 values output in the DAC.  And with an MCLK of 125Mhz, that will only happen when a desired frequency of less than 122,070.3125Hz has been selected.  Any higher than that, all POSSIBLE values in the DAC won't get hit each and every time thru the sequence.  They might get hit eventually, but not on each cycle of the outputted sine wave.

So, that was quite a long post, but if there was any point you were trying to make, you didn't make it. Other than the point that you may want to brush up your filtering basics (and tone down your language), which I was trying to point out to you from the very beginning. What you said in that last post was mostly correct, but not very relevant. As hamster_nz and tggzzz showed very clearly, the reconstruction (or anti alias) filter is the real "point".

And this may all be an "elite" discussion, but I think it's still quite good to have it, because it boils down to knowing what filtering can do for you, and this is an important topic in electronics - those who fail to grasp it will make a lot of incorrect conclusions. This is the exact topic that the "high-res music" audiophools often fail to understand, when they come up with similarly flawed explanations about stair steps, etc.

Found this with some more scope pictures, though not at 30MHz: http://nr8o.dhlpilotcentral.com/?p=83

You may also want to refer to this nice DSP book, and this page in particular: http://www.dspguide.com/ch3/3.htm. Have a good look especially at Figure 3-6. "As just described, the original analog signal can be perfectly reconstructed by passing this impulse train through a low-pass filter, with the cutoff frequency equal to one-half of the sampling rate." Also check out the "myths" at the bottom.

[Mechatrommer]

AD9850 always uses the 125Mhz MCLK (or whatever Mhz is going in there) as the source for the accumulator....

nice theory explanation, but how are you going to explain hamster's (picture) case? lets assume his AD5541A is using 125MHz clock. he's outputting 1315789 / 8 = 164.473625KHz. i assume lookup table's values are not dynamically changed, they are fixed from factory arent they?

[c4757p]

It's not going to change the clock frequency, Mecha. I feel like you have no idea what you're talking about.

so what is it that you know what you are talking about? that you involved in the design that you didnt tell us? its either clock at 125MHz and keep the same table value for 125 clock count, or prescale the clock. either way, its not going to use different 1023 values throughout a period just as the picture says. thats my best guess, so what exactly it is? it will be usefull if you can shed the light, otherwise, i am right.

Read reply 61. And then read it again. Perhaps spend some time with the Google results for "DDS" too?

[tggzzz]

It's not going to change the clock frequency, Mecha. I feel like you have no idea what you're talking about.

so what is it that you know what you are talking about? that you involved in the design that you didnt tell us? its either clock at 125MHz and keep the same table value for 125 clock count, or prescale the clock. either way, its not going to use different 1023 values throughout a period just as the picture says. thats my best guess, so what exactly it is? it will be usefull if you can shed the light, otherwise, i am right.

Read reply 61. And then read it again. Perhaps spend some time with the Google results for "DDS" too?

And, for good measure, add reply #61 , thus: edit: it should, of course be reply #64, sigh

If I gave you a repeating series of repeating numbers 0,  1, 0. -1 and asked you what signal those samples represent, what would you say?
If I then gave you this repeating series 0.707, 0.707, -0.707, -0.707 and asked the same question, what would you say that was?
In both cases you would be right, but I could produce another signal that would sample giving exactly the same values..  Without additional information you don't have enough to uniquely identify and be able to reproduce the original signal.
However if I also add that the signal contains no frequency components over half the sample rate, then both series uniquely describe the same wave (a sine wave of the same amplitude) - there is no waveform other than a sine at a quarter the sample rate that will give you those numbers. (Of course with the difference is in the phase).

Assuming you are using a simple DAC (not a one-bit or oversampling one) doesn't matter how many samples you use per cycle of the output signal, as long as you play back more that two and have the correct reconstruction filter then the information is all in there to recreate a signal that faithfully represents the original to the limits of the DAC's resolution.

[sync]

I think amplitude is dropped becouse i haven't used any external filters and high speed amplifiers , i want to design an output filtering stage what do you recommend me ,can iuse zero crossing detector at output to get square wave output ? And which op amp should i have to use for at least 40 mhz bw?

I saw in your video that you are using a 3.5mm phone jack for output. These are not well suited for high frequencies. Also audio cables won't work well. I'm guessing the amplitude drop is mainly caused by cabling.
Normally generators at these frequencies using 50ohm BNC connectors and coax cables. But then you should have an output amplifier/driver with 50ohm output impedance.

[Mechatrommer]

Read reply 61. And then read it again. Perhaps spend some time with the Google results for "DDS" too?

help the replier #61 to explain my confusion... how the accumulator can jump between lookup table.... we have 1024 entries (of one complete sine wave?), only 8 is used there jump from table(0) to table(128). accumulator keep adding at 125MHz rate, he's talking about 10bits MSB as lookup table entry. care to calculate for whats the tuning parm?

to be precise... table(0) is at accumulator value 2^22, table(1) is acc=2^22+1 and so on, what the tuning parameter that wont change 10MSB of acc for another 125 clock count, but when it got changed, the 10MSB will jump from table(0) (acc = 2^22) to table(128) (acc = 2^22+128)?

[tggzzz]

Read reply 61. And then read it again. Perhaps spend some time with the Google results for "DDS" too?

help the replier #61 to explain my confusion... how the accumulator can jump between lookup table.... we have 1024 entries (of one complete sine wave?), only 8 is used there jump from table(0) to table(128). accumulator keep adding at 125MHz rate, he's talking about 10bits MSB as lookup table entry. care to calculate for whats the tuning parm?

I'm sorry, I have no idea what you are trying to say and ask.

I suggest that if you write thing down carefully then maybe you will understand your question and be able to answer to, or at least it would give us a chance.

[Mechatrommer]

i mean the nice theory

I'm sorry, I have no idea what you are trying to say and ask.

i've added detailed explanation above pls refresh and reread... in the mean time i'll polish again the "basic dds" if i can re-shed some light...
http://www.ni.com/white-paper/5516/en/

[tggzzz]

Read reply 61. And then read it again. Perhaps spend some time with the Google results for "DDS" too?

help the replier #61 to explain my confusion... how the accumulator can jump between lookup table.... we have 1024 entries (of one complete sine wave?), only 8 is used there jump from table(0) to table(128). accumulator keep adding at 125MHz rate, he's talking about 10bits MSB as lookup table entry. care to calculate for whats the tuning parm?

to be precise... table(0) is at accumulator value 2^22, table(1) is acc=2^22+1 and so on, what the tuning parameter that wont change 10MSB of acc for another 125 clock count, but when it got changed, the 10MSB will jump from table(0) (acc = 2^22) to table(128) (acc = 2^22+128)?

Take the time to use a piece of graph paper to work through the example posed in reply #64, viz:

I lost what I started but tund at 30MHz  a 125MHz clock every 25 wave will look alike, with different distortions on the other 24 waves with some being affected badly in amplitude because of the aliasing between the 125MHz clock and thet lookup table to get the 30MHz signal, but I didn't examine the datasheet in detail.

If I gave you a repeating series of repeating numbers 0,  1, 0. -1 and asked you what signal those samples represent, what would you say?

If I then gave you this repeating series 0.707, 0.707, -0.707, -0.707 and asked the same question, what would you say that was?

In both cases you would be right, but I could produce another signal that would sample giving exactly the same values..  Without additional information you don't have enough to uniquely identify and be able to reproduce the original signal.

However if I also add that the signal contains no frequency components over half the sample rate, then both series uniquely describe the same wave (a sine wave of the same amplitude) - there is no waveform other than a sine at a quarter the sample rate that will give you those numbers. (Of course with the difference is in the phase).

Plot those points on the same graph, and draw some lines through them for each of the 4 cases (2 lines, infinite/finite bandwidth).