30 MHZ ad9850 DDS Signal Generator in 12$

[Kedar264]

An Precession Signal generator is very easy and affordable make using an arduino and dds synthesizer (ad9850) .

You can make decent 0 -30 MHZ frequency Signal generator only in 12$ . If you are pro over clocker then 40MHZ in same price .

See the video
  https://youtu.be/1SgcjxacGlQ

You will need frequency generator if you are a amateur radio guy or hobbyist or professional electronic guy.

 Here's  Part list you will need
1. Arduino Pro mini
2.AD9850  (DDS Synthesizer)
3.16×2 LCD Display  ( Hitachi hd 44780 )
4.Rotary Encoder


#CODE LIBRARY AND SCHEMATICS

http://www.mediafire.com/?vn3xfn956k12g

Here's  Few scope shots with 1,10,20 and 30 mhz

[moffy]

Thanks.

[Kedar264]

 

[Skimask]

And when you get it up to around 30Mhz, look at the actual output on an o'scope and see how much it really looks like shit.

[coppice]

And when you get it up to around 30Mhz, look at the actual output on an o'scope and see how much it really looks like shit.

How the signal looks at 30MHz will depend entirely on the quality of filtering used at the output of the DDS chip. The OP's schematic doesn't show any filtering.

[Rerouter]

the conventional ebay modules have a poor filter set at the wrong cutoff frequency, doesnt bother me in the slightest considering i am using it for up to 25Khz with fractional hz adjustment,

[Skimask]

Even with filtering, point is that those modules generally use a 125Mhz xtal.  30Mhz sine wave with a 125Mhz MCLK will give a guy, what, 4.x bits of DAC resolution, give or take...
Sine wave ends up looking like sticky spaghetti thrown on a wall.

[niekvs]

Even with filtering, point is that those modules generally use a 125Mhz xtal.  30Mhz sine wave with a 125Mhz MCLK will give a guy, what, 4.x bits of DAC resolution, give or take...
Sine wave ends up looking like sticky spaghetti thrown on a wall.

Can you elaborate? Why wouldn't this DDS chip be able to generate a 30MHz sine wave when fed by a 125MHz crystal? From the datasheet: "The AD9850’s circuit architecture allows the generation of output frequencies of up to one-half the reference clock frequency (or 62.5 MHz)". Even a square wave will be a perfect sine wave after proper low-pass filtering. Look at page 9 of the datasheet to see some of the aliasing that occurs, which is spaced out far enough for easy low-pass filtering.

Admittedly, the original post has a schematic without any filtering, but even that would probably show up as a perfect sine at 30MHz on most people's Rigol DS1052 limited to 50MHz

[Kleinstein]

The AD9850 has a 10 Bit DAC. So Distortion is not that bad. The principle limit of the DDS is at half the sampling frequency. With a real filter, something like 1/3 of the sampling frequency is a realistic upper limit. However this at least needs the filter components to be chosen correctly and a reasonable HF layout.

So if the filter is correctly build, a 30 MHz Signal can still look good. Still it's a good idea to check it - it may be OK, but it may also show quite some aliases. It depends on the type of module used.

[Kedar264]

Soon i will upload a video sshowing its response, but for a beginner its useful for such budget considering other similar products.

[Kedar264]

Soon i will upload a video showing its response, but you can get idea from these scope shots ,for a beginner its useful for such budget considering other similar products.

[niekvs]

Nice. I hadn't expected it to look bad. Not sure what the other guy meant with his comments about that it would look like "shit" or "spaghetti". I guess perhaps he wouldn't know any better considering he's a guy who prefers not to take things apart, but turn them on

[Kleinstein]

The waveform looks OK, but the amplitude is going down quite a lot. So it looks like the filter is setting in to low. The way the output is connected may influence the filter as well. How are the data measured ?

Without an appropriate output filter, the signal may look rather strange, possibly like a more or less random up and down close to the upper frequency limit, as one has a mixture of the frequency one wants and something like the sampling frequency +- the set frequency.

There are two thing missing to make a useful function generator: A slightly more powerful output amplifier, so you can get something like a few volts into 50 Ohm would be very useful. Also a defined attenuator to set the amplitude to lower levels if needed is commonly expected.

[sync]

Nice. I hadn't expected it to look bad. Not sure what the other guy meant with his comments about that it would look like "shit" or "spaghetti". I guess perhaps he wouldn't know any better considering he's a guy who prefers not to take things apart, but turn them on

The system (generator + cabling + scope) has a little bit more than 10MHz bandwidth. At 1MHz the peak-to-peak voltage is 1.06V. At 10MHz only 784mV. That's near the -3dB point. With such a low bandwidth (low pass filter) every waveform at 30MHz looks like a good sine wave.

I looked at one of these Ebay AD9850 modules with 100+ MHz bandwidth. At 30MHz the waveform didn't look nice anymore.

[Skimask]

Nice. I hadn't expected it to look bad. Not sure what the other guy meant with his comments about that it would look like "shit" or "spaghetti". I guess perhaps he wouldn't know any better considering he's a guy who prefers not to take things apart, but turn them on

Nice...try again.
Run those waveforms thru a spec-an and see what numbers you come up with.
30Mhz looks more of a triangle.

[Mechatrommer]

it may not run perfectly fine at >30MHz for some people, but at $12 say 10MHz BW limited, it may be the best bang/buck for most poormen approach. and the OP hasnt yet put any filtering and front end output just like other more robust and expensive DDS units. so sure there are alot to improve on this one. otoh i like the idea of push button to switch between freq increment range.

[Skimask]

Don't get me wrong.  I've got 6 of these AD9850 modules laying around in various forms, in use as variable square wave makers, hacked up as signal generators, etc.
But I also don't expect them to make decent high freq waveforms either.
Like most other things on chinabay, to say that they can do 30Mhz is quite a stretch of the imagination.

[Mechatrommer]

they maybe overspecify it, but say from testing it got 10MHz BW in reality... still alot cheaper than a standard 10MHz FG made in "not china". granted they have all built in, but some people just dont have the bill.

[sync]

The modules have much more bandwidth than 10MHz. In reality the modules I got have too much bandwidth (filter for AD9851 at ~70MHz). The 10MHz bandwidth is caused by other things.
These modules are nice. But don't expect wonders.

[niekvs]

Nice...try again.
Run those waveforms thru a spec-an and see what numbers you come up with.
30Mhz looks more of a triangle.

That probably means the filtering wasn't done properly on these modules (or by issues in the way it's measured, as mentioned above), which is also evident by the attenuation seen in the plots.

Even with filtering, point is that those modules generally use a 125Mhz xtal.  30Mhz sine wave with a 125Mhz MCLK will give a guy, what, 4.x bits of DAC resolution, give or take...

I still don't see what you're trying to say with the above statement, about 4.x of DAC resolution? The AD9850 has a 10 bit DAC. And proper filtering should remove any alias images or harmonics, resulting in a sine wave. Again, if you look at page 9 of the datasheet (http://www.analog.com/media/en/technical-documentation/data-sheets/AD9850.pdf), you'll see that the images should be low pass filtered, after which only the fundamental (sine) remains.

[Skimask]

I still don't see what you're trying to say with the above statement, about 4.x of DAC resolution? The AD9850 has a 10 bit DAC. And proper filtering should remove any alias images or harmonics, resulting in a sine wave. Again, if you look at page 9 of the datasheet (http://www.analog.com/media/en/technical-documentation/data-sheets/AD9850.pdf), you'll see that the images should be low pass filtered, after which only the fundamental (sine) remains.

Works nice...in theory...

4.x BITS of DAC resolution, call it 4 bits if the X bothers you.  (Note...I actually meant 2.x)
MCLK runs at 125Mhz.  You want 30Mhz output.  You have to add to the accumulator a number that'll swing the DAC fast enough to give you that 30Mhz output, and it has to be a large number.  As the desired output frequency gets higher, the number of 'steps' in your output drops.
Say you want a 62.5Mhz sine wave output.  Well, it ain't gonna happen.  125Mhz / 62.5Mhz = 2 steps, high and low.  1 bit sine wave = square wave.  Filter that...
Want a 31.25 sine wave output?  Ain't gonna happen again. 125Mhz / 31.25Mhz = 4 steps, high, 1/2 high, 1/2 low, and low.  2 bit sine wave?  No...
You want the full 10 bit DAC resolution, you have to divide your MCLK by 1024...125Mhz / 1024 = 122,075.3125 Hz.  Double the Hz for every bit you can stand to lose in DAC resolution.

Simple math.

As far as filtering goes...  Sure...design all the filters you want.  Try it at 30Mhz and you'll end up with garbage.  Even if you do get a decent sine wave output that's free of distortion, it'll likely only work well within a very narrow set of parameters.
Sure...go ahead and buffer the output of that filter.  Sounds good.  By the time you get done with all of that, may as well have gone and bought a proper 30Mhz sine wave generator.

[retrolefty]

Too much elitism going on here. This is a great project for a DIY beginner offering access to a very basic RF generator that so many would not be able to or wanting to make the investment needed to get started on serious RF learning.

 I so wish such tech was available when I started in ham radio in the 70s, it would have helped many of my early 'learning' RF projects. It would be cool to see several examples built by different people, and any changes or additions offered up.  I would think an external amplifier with AGC limiting would be a good candidate?

 

[sync]

An amplifier and AGC circuit would be nice. For >20MHz I only have these modules.
btw: I fixed the 30MHz issue by overclocking (200MHz).

[paulie]

Well, it ain't gonna happen.  125Mhz / 62.5Mhz = 2 steps, high and low.  1 bit sine wave = square wave.  Filter that...

I need to tell you a secret. Inside every square wave there is a 100% pure sine wave struggling to overcome social stereotypes and break out of the closet. Only 10 cents of components required to do so. The real problem is unless those numbers in your example are exact it does not result in actual square wave due to alias and other factors.

[Skimask]

Look...I'm not saying the damn things won't do 30Mhz.  I'm saying they won't do a nice, distortion free 30Mhz.  Plain and simple.  Nor will those $12 modules get anywhere near it.
Overclocking...ok, sure, maybe you can get away with it.  Maybe not.  Iffy at best.  The AD9851 is rated for 180Mhz, same thing with an extra 55Mhz of headroom on the Xtal input.  Probably a binned AD9850 anyways.  Might be able to overclock that too.  Yay!
Yes, square wave composed of sine waves...ok fine.  No kidding.  Also assumes you have a nice distortion free square wave to begin with...which you won't...which will give you nice distorted sine waves at the output...which you will.

[Kleinstein]

With a correct filter the AD9850 is well capably to produce a decent 30 MHz signal. The datasheet even quotes performance at 40 MHz.

Its also possible to get a low distortion square wave from the sine, not the other way around.

[Skimask]

With a correct filter the AD9850 is well capably to produce a decent 30 MHz signal. The datasheet even quotes performance at 40 MHz.

And only at 30Mhz (or 40Mhz), and practically nowhere else.  Kinda defeats the purpose of having an adjustable frequency.
Decent...usable...maybe.  Distortion free...no.

[niekvs]

Say you want a 62.5Mhz sine wave output.  Well, it ain't gonna happen.  125Mhz / 62.5Mhz = 2 steps, high and low.  1 bit sine wave = square wave.  Filter that...
Want a 31.25 sine wave output?  Ain't gonna happen again. 125Mhz / 31.25Mhz = 4 steps, high, 1/2 high, 1/2 low, and low.  2 bit sine wave?  No...

Maybe you should go over your DSP/filtering basics. "Filter that", well that's why I was referring you to page 9 (and 8 ) of the datasheet: it will show you how to do it.

And this whole thing about 4 bits of DAC resolution still makes no sense. The part has a 10 bits DAC. It's not "2 steps, high and low", but 2^10 (1024) possible values. They will vary in phase, and so vary in amplitude, as the frequency won't be an exact multiple.

It's well possible that this particular module (not the AD9850) didn't do the filtering right - I heard somewhere that it has a 90MHz filter instead of the 42MHz one shown in the datasheet. This could explain why at 30MHz there may be some distortion from the 1st image, which would sit at 125MHz - 30MHz = 95MHz (assuming the filter doesn't have a very steep roll off).

Another issue with your bad experience with your modules may be the way you measured them. Other than the amplitude issue (which may be related to unintended filtering), the sine actually looks quite good even at 30MHz on the images given earlier.

[retrolefty]

With a correct filter the AD9850 is well capably to produce a decent 30 MHz signal. The datasheet even quotes performance at 40 MHz.

And only at 30Mhz (or 40Mhz), and practically nowhere else.  Kinda defeats the purpose of having an adjustable frequency.
Decent...usable...maybe.  Distortion free...no.

 Is "distortion free" a requirement for a $12 project? Again why must projects of this scope have to go through elite approval? Or maybe many of these comments are about ego and not helping people.



 

[niekvs]

Considering he went from "it really looks like shit", "garbage" and "spaghetti thrown on the wall" to "Decent...usable...maybe", I guess we can assume he realized he was a bit quick to judge this project   

[Skimask]

Nope...
"really looks like shit" doesn't mean it's not usable.  Put it thru a comparator and get a square wave out of it.  Usable.  Or just use the square wave output.

Ain't no damn elite approval going on here.  FOK!  I'm as dumb as the next dipshit down the line.
People read the chinabay header that says 30Mhz signal generator.  They buy it and wonder why it puts out shit at 30Mhz.  Then go out in the wild and bitch about shitty equipment when the problem in the first place is shitty equipment sold as good stuff.

DSP/filtering basics/10bit DAC - I've got plenty of those laying around in my head.  No need to go back to basics.
Yes, the part has a 10-bit DAC.  No, you will not and cannot possibly use all 10 bits in each 360 degrees of an output sine wave once you get above certain frequencies.
Again, if you have an MCLK of 125Mhz, which most of these modules do, and you want to output a sine wave at 62.5Mhz, you will get an output that is a square wave, effectively a 1-bit DAC.  Plain and simple.  Don't believe me?  Try it and see what happens.
If you want an output of 31.25Mhz, you will get an output that is a stepped-square wave with only 4 points, effectively a 2-bit DAC.
If you want an output sine wave of X frequency that does not divide into 125Mhz perfectly, then you will get a stepped output that varies from cycle-to-cycle.  Depending on the frequency desired, will you be able to see those steps?  Maybe, maybe not.  Depends how high the frequency is.
I might even humor this thread with a video eventually.

[paulie]

They buy it and wonder why it puts out shit at 30Mhz.

Probably not. I think vast majority of buyers will not use it for 30mhz and the few who do will never suspect anything at all wrong. Even with minimal filter any odd harmonics will be way down and even if not most applications will ignore.

Regarding egos I love those. Pop in the toaster and 1 minute later... yummmmmmmm.

[niekvs]

If you want an output of 31.25Mhz, you will get an output that is a stepped-square wave with only 4 points, effectively a 2-bit DAC.
If you want an output sine wave of X frequency that does not divide into 125Mhz perfectly, then you will get a stepped output that varies from cycle-to-cycle.  Depending on the frequency desired, will you be able to see those steps?

Not "effectively a 2-bit DAC" - these 4 points will be the exact points out of 1024 that they mathematically should be. If it would be a 2-bit DAC, they would be quantized to one of 4 values, not one of 1024. But disregarding this, there's only one bandlimited signal that will pass through these 4 points, and that's the 31.25MHz sine. Not some "triangle" wave, but a sine. If it's not a sine, it's not filtered right.

"I might even humor this thread with a video eventually."

Please do, I'm curious about your test setup: just make sure to use a proper filter (and a scope with high enough bandwidth)

[Tac Eht Xilef]

Without particularly wanting to buy into this argument (I'm pretty familar with both the AD9850 & these modules as well as other AD DDS chips at HF frequencies, and largely agree with Skimask), you guys are aware that AD have a web-based DDS simulator aren't you?

All arguments about simulators aside, in my experience it's remarkably accurate - I've used it to check both the raw DDS output & planned filter designs, and what it shows is pretty much exactly what I've seen on the scope & SA in the real world. Dial up an AD9850 with 125MHz clock and play with it for yourselves.

Note that unchecking the filter response checkbox doesnt turn the filter off; you have to click 'configure' and choose a filter topology of 'off'...

A few other observations:

• Every one of those modules I've seen with a 125MHz clock has a 3.3v oscillator. Conversely, the AD9850 is only specced to (I think) 100MHz clock @ 3.3v. Depending what voltage you run it at, one or the other is being abused...
• The OP's project is nothing new - it's pretty much a "My First Arduino and DDS" project, and there must be 1000's of them out there by now. That's not to take away from it, but it's not amazingly unique by any means.
• About 1/2 of the AD9850 modules I've seen are reluctant to go into serial data mode under serial control - they should really be hard-configured into serial mode by pulling the appropriate // data pins hi & low as per the datasheet.
  
• As sync said upthread, what's missing from almost all of them is AGC & a buffer / driver amp. That, and a simple attenuator stage, would make it a pretty decent project. (I've had that on my backburner for a couple of years now, and I still haven't gotten around to it...)

[Sparc]

Nope...
"really looks like shit" doesn't mean it's not usable.  Put it thru a comparator and get a square wave out of it.  Usable.  Or just use the square wave output.

Ain't no damn elite approval going on here.  FOK!  I'm as dumb as the next dipshit down the line.
People read the chinabay header that says 30Mhz signal generator.  They buy it and wonder why it puts out shit at 30Mhz.  Then go out in the wild and bitch about shitty equipment when the problem in the first place is shitty equipment sold as good stuff.

DSP/filtering basics/10bit DAC - I've got plenty of those laying around in my head.  No need to go back to basics.
Yes, the part has a 10-bit DAC.  No, you will not and cannot possibly use all 10 bits in each 360 degrees of an output sine wave once you get above certain frequencies.
Again, if you have an MCLK of 125Mhz, which most of these modules do, and you want to output a sine wave at 62.5Mhz, you will get an output that is a square wave, effectively a 1-bit DAC.  Plain and simple.  Don't believe me?  Try it and see what happens.
If you want an output of 31.25Mhz, you will get an output that is a stepped-square wave with only 4 points, effectively a 2-bit DAC.
If you want an output sine wave of X frequency that does not divide into 125Mhz perfectly, then you will get a stepped output that varies from cycle-to-cycle.  Depending on the frequency desired, will you be able to see those steps?  Maybe, maybe not.  Depends how high the frequency is.
I might even humor this thread with a video eventually.

This explanation sounds wrong.  There is a confusion between DAC bit depth and sample rate.   I think this confusion might come from the audio-phile community.  People who say you need super high sample rates to get quality audio from your digital audio gear.  They think we need 192 khz audio systems.   By your explanation, a CD player could only give 16 bit quality at 44100/65536= 0.67 hz.    Whether you use all 2^N possible steps in a cycle is irrelevant, you actually get all bits up to nyquest frequency. 

There are other reasons to criticize the cheap AD9850 modules from Ebay.   The filter cutoff is at the wrong frequency, the 125mhz oscillator most likely isn't rated for 5V operation, maybe the AD9850 chips are factory rejects.   This has been pointed out in this thread and others. 

If you want a nice video demonstration of sampling and the so-called "stair step" problem, check out this video demonstration.   Its with audio frequencies, but the principles are the same.

article:
http://wiki.xiph.org/Digital_Show_and_Tell/Episode_02

video:
http://www.xiph.org/video/vid2.shtml

[tggzzz]

Nope...
"really looks like shit" doesn't mean it's not usable.  Put it thru a comparator and get a square wave out of it.  Usable.  Or just use the square wave output.

Ain't no damn elite approval going on here.  FOK!  I'm as dumb as the next dipshit down the line.
People read the chinabay header that says 30Mhz signal generator.  They buy it and wonder why it puts out shit at 30Mhz.  Then go out in the wild and bitch about shitty equipment when the problem in the first place is shitty equipment sold as good stuff.

DSP/filtering basics/10bit DAC - I've got plenty of those laying around in my head.  No need to go back to basics.
Yes, the part has a 10-bit DAC.  No, you will not and cannot possibly use all 10 bits in each 360 degrees of an output sine wave once you get above certain frequencies.
Again, if you have an MCLK of 125Mhz, which most of these modules do, and you want to output a sine wave at 62.5Mhz, you will get an output that is a square wave, effectively a 1-bit DAC.  Plain and simple.  Don't believe me?  Try it and see what happens.
If you want an output of 31.25Mhz, you will get an output that is a stepped-square wave with only 4 points, effectively a 2-bit DAC.
If you want an output sine wave of X frequency that does not divide into 125Mhz perfectly, then you will get a stepped output that varies from cycle-to-cycle.  Depending on the frequency desired, will you be able to see those steps?  Maybe, maybe not.  Depends how high the frequency is.
I might even humor this thread with a video eventually.

You have bothered to read the AD9850 data sheet haven't you?

Figure 17 shows a 42MHz 7th order elliptic LPF which will do a pretty good job of eliminating harmonics of a 125MHz clock. Now it won't be "zero distortion", of course, but then nothing is zero distortion!

In my experience a more significant point is that if the comparator is connected to the LPF output (in order to get a 50% duty cycle square wave), then the comparator will introduce glitches onto the sine wave output.

[Kedar264]

And when you get it up to around 30Mhz, look at the actual output on an o'scope and see how much it really looks like shit.

See the scop shot

[c4757p]

And when you get it up to around 30Mhz, look at the actual output on an o'scope and see how much it really looks like shit.

See the scop shot

First, that looks terrible, it looks like a triangle wave. Second, it looks like you're running out of bandwidth, what's that scope do? You need a lot of bandwidth overhead to measure the purity of a sine wave.

Edit: wait... does the circled (20) at the bottom mean you've got the 20 MHz bandwidth limit switched on?

[Kedar264]

The waveform looks OK, but the amplitude is going down quite a lot. So it looks like the filter is setting in to low. The way the output is connected may influence the filter as well. How are the data measured ?

What possible filters should i use?

Without an appropriate output filter, the signal may look rather strange, possibly like a more or less random up and down close to the upper frequency limit, as one has a mixture of the frequency one wants and something like the sampling frequency +- the set frequency.

There are two thing missing to make a useful function generator: A slightly more powerful output amplifier, so you can get something like a few volts into 50 Ohm would be very useful. Also a defined attenuator to set the amplitude to lower levels if needed is commonly expected.

[Kedar264]

Actually at 30 mhz i made mistake  (my scope's 20 mhz bw limit is on ) here is proper scope shot with bw limit turned off.

[Bud]

ADI says they use lookup table to drive the DDS DAC, so no, it is not like 1-bit DAC when frequency approaches Fclk/2, regardless of frequency it always outputs levels with whatever DAC resolution is (the lookup table is driven by phase information and is the same for any frequency). Less steps - yes, and that is the job of the anti-aliasing filter to filter out aliases. Therefore any of the DDS signal gen design that does not have some sort of a output filter is deficient.

EDIT: deficient if the goal is to generate sinewave. For some special applications filtering may not be required and even undesired.

@Kedar264
your screenshot is incorrect on several counts. Just the amplitude alone will not drop that much at 30MHz. Either your scope has a bandwidth filter switched on as the other poster said, or the scope itself has small bandwidth.

EDIT: I was typing when you posted your last screenshot but it still does not look right. Amplitude should not drop by 10dB at just 25% of F clock. What scope model do you use?

[Kedar264]

My scope is Hantek DSO 5072P it has  70 MHZ Bandwidth   

[c4757p]

70 MHz isn't enough for a 30 MHz sine wave, that only gets you up to the 2nd harmonic. I'd probably want to shoot for bandwidth up to the tenth harmonic, or 300 MHz. (However, for what it's worth that does look much better with the limit switched off.)

[Kedar264]

I think amplitude is dropped becouse i haven't used any external filters and high speed amplifiers , i want to design an output filtering stage what do you recommend me ,can iuse zero crossing detector at output to get square wave output ? And which op amp should i have to use for at least 40 mhz bw?

[Bud]

Yes looks the scope performed the function of anti-aliasing filter. For F clck=125MHz and 30MHz output you need at least  150 MHz scope bandwidth to see effect of aliases (Fclk - Fout, Fclk + Fout)

[Bud]

I think amplitude is dropped becouse i haven't used any external filters and high speed amplifiers

No, I recommend you go to ADI web site and play with their DDS tool as the other reader suggested, to understand amplitude and spectrum of a DDS. This may become an exciting jorney for you to learn this stuff.

[hamster_nz]

...and that is the job of the anti-aliasing filter to filter out aliases. Therefore any of the DDS signal gen design that does not have some sort of a output filter is deficient.

What do you mean by "deficient"? If you mean "lacking" then yes, any DDS signal gen that does not have an output filter is lacking an output filter.

And what are these anti-aliasing filters for DACs you talk of? On the output there is no way to generate aliases, as aliasing is an effect that causes different signals to become indistinguishable (or aliases of one another) when sampled.

Would you be talking of the reconstruction filter (http://en.wikipedia.org/wiki/Reconstruction_filter) that removes any high frequency noise in the reconstructed signal, and compensates for the inherent limitations of conversion process?

[hamster_nz]

Oh, and as an illustration,  here is what the output of a DAC looks like without a reconstruction filter.



And here is what it looks like, once filtered



However, in this case I didn't use an output filter on the DAC, I used the bandwidth filter on my scope. Everything that makes it look "un-sine-like" and "steppy" is just high frequency noise... it isn't aliases. You can't filter out  aliases without also reducing the desired signal too.

[Bud]

What do you mean by "deficient"? If you mean "lacking" then yes,

You got it. Sorry for using a fancy word. Lets see what Webster dictionary says:

"Deficiency: a lack of something that is needed : the state of not having enough of something necessary"

And what are these anti-aliasing filters for DACs you talk of? On the output there is no way to generate aliases, as aliasing is an effect that causes different signals to become indistinguishable (or aliases of one another) when sampled.

I know what you mean but in DDS literature Aliases mean frequency components Fclock plus minus Fout. They can be filtered out and they even can be filtered in (so to speak) or selected to become the DDS signal gen output. This is described in practically any Analog Devices DDS datasheet. Try opening AD9850 datasheet for example and search for all instances of "alias", see what you can learn.

[Bud]

Everything that makes it look "un-sine-like" and "steppy" is just high frequency noise... it isn't aliases. You can't filter out  aliases without also reducing the desired signal too.

As I pointed out yes you can filter aliases out or select a particular aliased component. You can check ADI DDS datasheets for explanation.

Your first screenshot is good and shows enough bandwidth and since aliases are part of an unfiltered DDS spectrum, that waveform includes aliases too. Noise would manifest itself as a random component, but the steps on the waveform are not random.

[hamster_nz]

I know what you mean but in DDS literature Aliases mean frequency components Fclock plus minus Fout. They can be filtered out and they even can be filtered in (so to speak) or selected to become the DDS signal gen output. This is described in practically any Analog Devices DDS datasheet. Try opening AD9850 datasheet for example and search for all instances of "alias", see what you can learn.

I just did read the datasheet - (alias appears only 6 times, all on page 9 ) - and I did learn one thing. It must be a local AD terminology thing (or maybe USA vs "the world" thing) - as they refer to adding "alias filters" on DAC, which removes any undesirable out-of band signals on the ADC output.  They definitely DO NOT not have an anti-alias filter on the DAC output.

Where I'm from these DAC output filters are usually referred to as "reconstruction filters" (which can actually do a little more than an alias filter) or ""anti-imaging filters".

Shrug, must be a geographic/cultural thing.

[Kedar264]

I almost forgot to mention ad9850 has 4 outputs 2 sine waves 90°phase shifted and 2 square waves .

[Mechatrommer]

Say you want a 62.5Mhz sine wave output.  Well, it ain't gonna happen.  125Mhz / 62.5Mhz = 2 steps, high and low.  1 bit sine wave = square wave.  Filter that...
Want a 31.25 sine wave output?  Ain't gonna happen again. 125Mhz / 31.25Mhz = 4 steps, high, 1/2 high, 1/2 low, and low.  2 bit sine wave?  No...

Maybe you should go over your DSP/filtering basics. "Filter that", well that's why I was referring you to page 9 (and 8 ) of the datasheet: it will show you how to do it.
And this whole thing about 4 bits of DAC resolution still makes no sense. The part has a 10 bits DAC. It's not "2 steps, high and low", but 2^10 (1024) possible values. They will vary in phase, and so vary in amplitude, as the frequency won't be an exact multiple.

the fact is, this thing is not a basic DSP thing. 125MHz clock is the max it can get to, the 10bit DAC is the max it can get to, but only at some  golden freq setting. at other freq, it will prescale the clock, use lesser bits etc through its definite DDS wisdom... at 62.5MHz, it cant use all 10bit dac because that way it will need around 64GHz of clocking 1023 data. at nyquist freq, it only can clock 2 points, hence 1 bit DAC usable.

take our fellow friend example...

if you look closely, it aint 125MHz clocking there, its 1MHz albeit it only generating 164KHz of signal, and only 2 bits (4 values) usable. so that proved there is a "definite wisdom" going on in the DDS., not the  basic DSP stuffs.

[miguelvp]

I don't think hamster was using the ad9850 he just mentioned a DAC and probably controlling the steps, most likely the DAC he was using could handle more resolution, but he was trying to make a point.

One thing about the ad9850 is that it will show those steps but not in a controlled way, meaning that the high frequency noise won't be distributed as nicely as in that example, so after applying filters not all the waves would be identical since the high frequency noise would be distributed over all the waves at different points.

But I think it's fine for up to 20MHz which is plenty, otherwise AD do offer other higher spec'd solutions.

[c4757p]

"definite wisdom"

 

[Mechatrommer]

maybe now you can start charting all the bits,clk,freq configuration just like hamster did, and tell us what exactly the formulation on how the DDS can output all the freq range, we have made observation on other DDS sometime ago. you tell us the formula and we can figure out what the "definite wisdom" is.

[hamster_nz]

I don't think hamster was using the ad9850 he just mentioned a DAC and probably controlling the steps, most likely the DAC he was using could handle more resolution, but he was trying to make a point.

- just there for illustration of an unfiltered DAC output.

It's actually a AD5541A , a 16-bit DAC, running an output sample frequency of 1,315,789 HZ. It is being driven by a lookup table of 1024 18-bit entries, with 8 bits of interpolation between entries (giving at worst +/- 1 LSB from a 2^18 entry lookup table feeding the 16-bit DAC). So it is close to perfect.  For that picture the generated frequency was 1/8th the sample frequency, so only 8 different values are being used.

The odd sample frequency has been chosen so I can generate frequencies in about 5 Hz steps (+/- 0.5%) for testing something I'm working on.

[Mechatrommer]

I don't think hamster was using the ad9850 he just mentioned a DAC and probably controlling the steps, most likely the DAC he was using could handle more resolution, but he was trying to make a point.

- just there for illustration of an unfiltered DAC output.
It's actually a AD5541A , a 16-bit DAC, running an output sample frequency of 1,315,789 HZ. It is being driven by a lookup table of 1024 18-bit entries, with 8 bits of interpolation between entries (giving at worst +/- 1 LSB from a 2^18 entry lookup table feeding the 16-bit DAC). So it is close to perfect.  For that picture the generated frequency was 1/8th the sample frequency, so only 8 different values are being used.
The odd sample frequency has been chosen so I can generate frequencies in about 5 Hz steps (+/- 0.5%) for testing something I'm working on.

the point that doesnt clear is that DDS wont use all 1024 lookup table, wont clock at max xtal clock everytime, as some might think just by looking at the datasheet...

[miguelvp]

It's actually a AD5541A , a 16-bit DAC, running an output sample frequency of 1,315,789 HZ.
...

damn I was going to say this:

Mearused: 1312500 (21 pulses in 16us) but I noticed it was doing 8 samples per wave so, 164.5K *8 = 1316000
Middle ground: 1314250

So I guessed 1315000 Hz and had it on my Notepad++ but thought it would be silly to share

[c4757p]

It's not going to change the clock frequency, Mecha. I feel like you have no idea what you're talking about.

[miguelvp]

I lost what I computed but tuned at 30MHz with a 125MHz clock every 25 wave will look alike, with different distortions on the other 24 waves with some being affected badly in amplitude because of the aliasing between the 125MHz clock and the lookup table to get the 30MHz signal, but I didn't examine the datasheet in detail.

[Skimask]

AD9850 always uses the 125Mhz MCLK (or whatever Mhz is going in there) as the source for the accumulator.  No random division going on, just straight up 125Mhz (again, or whatever a person is using for the MCLK).
125Mhz input, 32-bit "tuning word", which is the value that is added to the 32 bit accumulator, the upper 10 bits of which are fed to a sine wave loop up table, which in turn feeds the 10 bit output DAC.

Start off with zero's in everything...
You've got this 'tuning word', which is the adder, set it to a value of "1", just 1, not 0x01, just 1.
MCLK pulse comes in, add the value of the tuning word to the accumulator, accumulator = 1, nothing in the upper 10 bits yet (won't be for another 4MiB pulses)
Keep adding MCLK pulses at the rate of 125 million per second and this 32 bit accumulator will overflow in 34.359738368 seconds (125Mhz / 32bits), giving you an output frequency of 0.02910383045673370361328125 Hz.

Change the tuning word to 2,147,483,648 (2^31), the upper bit of the accumulator flips every MCLK pulse (it's an add, not a multiply, not a look up, just an add), the accumulator overflows, the overflow is thrown away.  But, the upper bit, 31, is also the upper bit of the 10 bit DAC.  Therefore, only 1 bit of the DAC is being used, the MSB.  Therefore, the output value only flips between 2 possible values, high and low.

Change the tuning word to 1,073,741,824 (2^30), the upper 2 bits of the accumulator change on every MCLK pulse.  The upper 2 bits, 30-31, also the upper 2 bits of the DAC.  Only 2 bits of the DAC is being used.  The output value only flips between 4 possible values.

So on down the line...

If the tuning word is less than 2^22 (total accumulator size - upper 10 bits, which again are the 10 bits of the output DAC), then and only then can you possibly get all 1024 values output in the DAC.  And with an MCLK of 125Mhz, that will only happen when a desired frequency of less than 122,070.3125Hz has been selected.  Any higher than that, all POSSIBLE values in the DAC won't get hit each and every time thru the sequence.  They might get hit eventually, but not on each cycle of the outputted sine wave.

What miguelvp said in the last post about being tuned to 30Mhz with a 125Mhz MCLK and every 25th wave being identical sounds about right, although I think it'll actually be every 6th wave will have identical characteristics...the other 5 waves will be fundamentally 30Mhz but with different distortions, harmonics, etc.

[miguelvp]

But I did notice one thing:

the output frequency can be digitally changed (asynchronously) at a rate of up to 23 million new frequencies per second

and

The device also provides five bits of digitally controlled phase modulation, which enables phase shifting of its output in increments of 180°, 90°, 45°, 22.5°, 11.25°, and any combination thereof

Surely that can help if the program driving the AD9850 takes advantage of that to compensate somehow, but I doubt that is used and not sure of the update rate for the phase shifting.

[Mechatrommer]

It's not going to change the clock frequency, Mecha. I feel like you have no idea what you're talking about.

so what is it that you know what you are talking about? that you involved in the design that you didnt tell us? its either clock at 125MHz and keep the same table value for 125 clock count, or prescale the clock. either way, its not going to use different 1023 values throughout a period just as the picture says. thats my best guess, so what exactly it is? it will be usefull if you can shed the light, otherwise, i am right.

[hamster_nz]

I lost what I started but tund at 30MHz  a 125MHz clock every 25 wave will look alike, with different distortions on the other 24 waves with some being affected badly in amplitude because of the aliasing between the 125MHz clock and thet lookup table to get the 30MHz signal, but I didn't examine the datasheet in detail.

If I gave you a repeating series of repeating numbers 0,  1, 0. -1 and asked you what signal those samples represent, what would you say?

If I then gave you this repeating series 0.707, 0.707, -0.707, -0.707 and asked the same question, what would you say that was?

In both cases you would be right, but I could produce another signal that would sample giving exactly the same values..  Without additional information you don't have enough to uniquely identify and be able to reproduce the original signal.

However if I also add that the signal contains no frequency components over half the sample rate, then both series uniquely describe the same wave (a sine wave of the same amplitude) - there is no waveform other than a sine at a quarter the sample rate that will give you those numbers. (Of course with the difference is in the phase).

Likewise, just because the 30MHz generated signal looks different during different cycles it is only because you have not yet put it through a proper reconstruction filter. block everything over 62.5MHz and it will look like a clean sine of constant amplitude - because it is a clean sine, with added noise (i.e. unwanted signal) that is outside of the 0 to 0.5 times the sample rate can be filtered off and discarded.

Assuming you are using a simple DAC (not a one-bit or oversampling one) doesn't matter how many samples you use per cycle of the output signal, as long as you play back more that two and have the correct reconstruction filter then the information is all in there to recreate a signal that faithfully represents the original to the limits of the DAC's resolution.

Of course sometimes getting the correct filter is hard (stop band being steep enough, ripple etc) so the best answer might be to properly double the sample rate in the digital domain, and use a faster DAC. 

[tggzzz]

If the tuning word is less than 2^22 (total accumulator size - upper 10 bits, which again are the 10 bits of the output DAC), then and only then can you possibly get all 1024 values output in the DAC.  And with an MCLK of 125Mhz, that will only happen when a desired frequency of less than 122,070.3125Hz has been selected.  Any higher than that, all POSSIBLE values in the DAC won't get hit each and every time thru the sequence. 

 The reconstruction filter will remove the higher frequencies, leaving only the sine wave below the cutoff frequency. The extent of the HF attenuation will, of course, be determined precisely by the reconstruction filter's "shape".

They might get hit eventually, but not on each cycle of the outputted sine wave.

Correct. So what? It isn't necessary for a value to be output on every cycle of a sine wave.

What miguelvp said in the last post about being tuned to 30Mhz with a 125Mhz MCLK and every 25th wave being identical sounds about right, although I think it'll actually be every 6th wave will have identical characteristics...the other 5 waves will be fundamentally 30Mhz but with different distortions, harmonics, etc.

True only if there is no reconstruction filter.

I get the feeling maths isn't your strong point, and that you don't understand fundamental sampling theory and fourier series. That's nothing to be ashamed of, but you might like to be aware of your limitations.

[niekvs]

If the tuning word is less than 2^22 (total accumulator size - upper 10 bits, which again are the 10 bits of the output DAC), then and only then can you possibly get all 1024 values output in the DAC.  And with an MCLK of 125Mhz, that will only happen when a desired frequency of less than 122,070.3125Hz has been selected.  Any higher than that, all POSSIBLE values in the DAC won't get hit each and every time thru the sequence.  They might get hit eventually, but not on each cycle of the outputted sine wave.

So, that was quite a long post, but if there was any point you were trying to make, you didn't make it. Other than the point that you may want to brush up your filtering basics (and tone down your language), which I was trying to point out to you from the very beginning. What you said in that last post was mostly correct, but not very relevant. As hamster_nz and tggzzz showed very clearly, the reconstruction (or anti alias) filter is the real "point".

And this may all be an "elite" discussion, but I think it's still quite good to have it, because it boils down to knowing what filtering can do for you, and this is an important topic in electronics - those who fail to grasp it will make a lot of incorrect conclusions. This is the exact topic that the "high-res music" audiophools often fail to understand, when they come up with similarly flawed explanations about stair steps, etc.

Found this with some more scope pictures, though not at 30MHz: http://nr8o.dhlpilotcentral.com/?p=83

You may also want to refer to this nice DSP book, and this page in particular: http://www.dspguide.com/ch3/3.htm. Have a good look especially at Figure 3-6. "As just described, the original analog signal can be perfectly reconstructed by passing this impulse train through a low-pass filter, with the cutoff frequency equal to one-half of the sampling rate." Also check out the "myths" at the bottom.

[Mechatrommer]

AD9850 always uses the 125Mhz MCLK (or whatever Mhz is going in there) as the source for the accumulator....

nice theory explanation, but how are you going to explain hamster's (picture) case? lets assume his AD5541A is using 125MHz clock. he's outputting 1315789 / 8 = 164.473625KHz. i assume lookup table's values are not dynamically changed, they are fixed from factory arent they?

[c4757p]

It's not going to change the clock frequency, Mecha. I feel like you have no idea what you're talking about.

so what is it that you know what you are talking about? that you involved in the design that you didnt tell us? its either clock at 125MHz and keep the same table value for 125 clock count, or prescale the clock. either way, its not going to use different 1023 values throughout a period just as the picture says. thats my best guess, so what exactly it is? it will be usefull if you can shed the light, otherwise, i am right.

Read reply 61. And then read it again. Perhaps spend some time with the Google results for "DDS" too?

[tggzzz]

It's not going to change the clock frequency, Mecha. I feel like you have no idea what you're talking about.

so what is it that you know what you are talking about? that you involved in the design that you didnt tell us? its either clock at 125MHz and keep the same table value for 125 clock count, or prescale the clock. either way, its not going to use different 1023 values throughout a period just as the picture says. thats my best guess, so what exactly it is? it will be usefull if you can shed the light, otherwise, i am right.

Read reply 61. And then read it again. Perhaps spend some time with the Google results for "DDS" too?

And, for good measure, add reply #61 , thus: edit: it should, of course be reply #64, sigh

If I gave you a repeating series of repeating numbers 0,  1, 0. -1 and asked you what signal those samples represent, what would you say?
If I then gave you this repeating series 0.707, 0.707, -0.707, -0.707 and asked the same question, what would you say that was?
In both cases you would be right, but I could produce another signal that would sample giving exactly the same values..  Without additional information you don't have enough to uniquely identify and be able to reproduce the original signal.
However if I also add that the signal contains no frequency components over half the sample rate, then both series uniquely describe the same wave (a sine wave of the same amplitude) - there is no waveform other than a sine at a quarter the sample rate that will give you those numbers. (Of course with the difference is in the phase).

Assuming you are using a simple DAC (not a one-bit or oversampling one) doesn't matter how many samples you use per cycle of the output signal, as long as you play back more that two and have the correct reconstruction filter then the information is all in there to recreate a signal that faithfully represents the original to the limits of the DAC's resolution.

[sync]

I think amplitude is dropped becouse i haven't used any external filters and high speed amplifiers , i want to design an output filtering stage what do you recommend me ,can iuse zero crossing detector at output to get square wave output ? And which op amp should i have to use for at least 40 mhz bw?

I saw in your video that you are using a 3.5mm phone jack for output. These are not well suited for high frequencies. Also audio cables won't work well. I'm guessing the amplitude drop is mainly caused by cabling.
Normally generators at these frequencies using 50ohm BNC connectors and coax cables. But then you should have an output amplifier/driver with 50ohm output impedance.

[Mechatrommer]

Read reply 61. And then read it again. Perhaps spend some time with the Google results for "DDS" too?

help the replier #61 to explain my confusion... how the accumulator can jump between lookup table.... we have 1024 entries (of one complete sine wave?), only 8 is used there jump from table(0) to table(128). accumulator keep adding at 125MHz rate, he's talking about 10bits MSB as lookup table entry. care to calculate for whats the tuning parm?

to be precise... table(0) is at accumulator value 2^22, table(1) is acc=2^22+1 and so on, what the tuning parameter that wont change 10MSB of acc for another 125 clock count, but when it got changed, the 10MSB will jump from table(0) (acc = 2^22) to table(128) (acc = 2^22+128)?

[tggzzz]

Read reply 61. And then read it again. Perhaps spend some time with the Google results for "DDS" too?

help the replier #61 to explain my confusion... how the accumulator can jump between lookup table.... we have 1024 entries (of one complete sine wave?), only 8 is used there jump from table(0) to table(128). accumulator keep adding at 125MHz rate, he's talking about 10bits MSB as lookup table entry. care to calculate for whats the tuning parm?

I'm sorry, I have no idea what you are trying to say and ask.

I suggest that if you write thing down carefully then maybe you will understand your question and be able to answer to, or at least it would give us a chance.

[Mechatrommer]

i mean the nice theory

I'm sorry, I have no idea what you are trying to say and ask.

i've added detailed explanation above pls refresh and reread... in the mean time i'll polish again the "basic dds" if i can re-shed some light...
http://www.ni.com/white-paper/5516/en/

[tggzzz]

Read reply 61. And then read it again. Perhaps spend some time with the Google results for "DDS" too?

help the replier #61 to explain my confusion... how the accumulator can jump between lookup table.... we have 1024 entries (of one complete sine wave?), only 8 is used there jump from table(0) to table(128). accumulator keep adding at 125MHz rate, he's talking about 10bits MSB as lookup table entry. care to calculate for whats the tuning parm?

to be precise... table(0) is at accumulator value 2^22, table(1) is acc=2^22+1 and so on, what the tuning parameter that wont change 10MSB of acc for another 125 clock count, but when it got changed, the 10MSB will jump from table(0) (acc = 2^22) to table(128) (acc = 2^22+128)?

Take the time to use a piece of graph paper to work through the example posed in reply #64, viz:

I lost what I started but tund at 30MHz  a 125MHz clock every 25 wave will look alike, with different distortions on the other 24 waves with some being affected badly in amplitude because of the aliasing between the 125MHz clock and thet lookup table to get the 30MHz signal, but I didn't examine the datasheet in detail.

If I gave you a repeating series of repeating numbers 0,  1, 0. -1 and asked you what signal those samples represent, what would you say?

If I then gave you this repeating series 0.707, 0.707, -0.707, -0.707 and asked the same question, what would you say that was?

In both cases you would be right, but I could produce another signal that would sample giving exactly the same values..  Without additional information you don't have enough to uniquely identify and be able to reproduce the original signal.

However if I also add that the signal contains no frequency components over half the sample rate, then both series uniquely describe the same wave (a sine wave of the same amplitude) - there is no waveform other than a sine at a quarter the sample rate that will give you those numbers. (Of course with the difference is in the phase).

Plot those points on the same graph, and draw some lines through them for each of the 4 cases (2 lines, infinite/finite bandwidth).

[Mechatrommer]

Plot those points on the same graph, and draw some lines through them for each of the 4 cases (2 lines, infinite/finite bandwidth).

i believe thats not what i was against to... i only asked to those of who that know what they are talking about. i initially lumped it as "definite wisdom" or "definite limited wisdom" to be more accurate? (check 2nd line my signature ) btw for the sake of it... let me check for those who know what they are talking the allknowing... here is from the ad9850 datasheet page 8

Code: [Select]

fOUT = (? Phase × CLKIN)/2^32
? Phase is the value of the 32-bit tuning word.
CLKIN=125MHz, calculating for the required 164KHz output, the tuning word will be 5634997 (the value is confirmed in the sim http://www.analog.com/designtools/en/simdds/dtDDSMain.aspx), i just run a homemade simulator to simulate accumulator increment and overflow... for each 125MHz clock, hence for each accumulator adding its value... (attached file, i only did 380 iteration or clk since my ide report overflow error no thanks to my 32bit machine) 14bits MSB just as stated in datasheet are separated by "-". here summary the first 5 iteration

Code: [Select]

00000000000000 - 000000000000000000
00000000010101 - 011111101110110101
00000000101010 - 111111011101101010
00000001000000 - 011111001100011111
00000001010101 - 111110111011010100

but from the the math it will need 2^32 / 5634997 = 762 iterations before accumulator wrapped around back to zero, so theoritically... ideally.... the DDS should be able to output 762 of distinct and different lookup table values, clocked, jumping up and down at 125MHz rate, visible on the scope unfiltered, right? but in practice.... it is not so.... here recap again...


8 values, clocked or changing value at 1MHz point whatever, WTF?. the all knowing said there's no prescale going on. so let me conclude with what i meant by "definite wisdom" is, encapsulated in the black box of...

Code: [Select]

The AD9850 uses an innovative and proprietary
algorithm that mathematically converts the 14-bit truncated
value of the phase accumulator to the appropriate COS value.
This unique algorithm uses a much reduced ROM look-up table
and DSP techniques to perform this function, which contributes
to the small size and low power dissipation of the AD9850.

ad9850 datasheet page 8...

but still... it really doesnt make any sense... 762 iterations but only 8 meaningfull values output
one may argue that the picture posted by hamster is from different dds, but its more robust dss compared to 9850, still output alot less than whats ideal...

[c4757p]

8 values, clocked or changing value at 1MHz point whatever, WTF?.

We've already established that this chip is not running at 125 MHz. Do the math again for 1 MHz. Hint: I don't think they're actually the same eight values, I think they're just close...

Another hint: If you divide the actual clock (1.315789 MHz) by the 164 kHz frequency, you get 8.02 ...

the all knowing said there's no prescale going on. so let me conclude with what i meant by "definite wisdom" is, encapsulated in the black box of...

Code: [Select]

The AD9850 uses an innovative and proprietary
algorithm that mathematically converts the 14-bit truncated
value of the phase accumulator to the appropriate COS value.
This unique algorithm uses a much reduced ROM look-up table
and DSP techniques to perform this function, which contributes
to the small size and low power dissipation of the AD9850.

ad9850 datasheet page 8...

That "black box" doesn't affect the signal, if it's doing what I think it's doing. It just takes advantage of the fact that a sinusoid is symmetric multiple ways to reduce duplication and make the lookup table smaller - it'll reconstruct the full sine wave using the "DSP techniques" they mention.

[Kalvin]

See message:
https://www.eevblog.com/forum/projects/30-mhz-ad9850-dds-signal-generator-in-12$/msg679821/#msg679821
"It's actually a AD5541A , a 16-bit DAC, running an output sample frequency of 1,315,789 HZ".

[Mechatrommer]

We've already established that this chip is not running at 125 MHz. Do the math again for 1 MHz.

no, in your respond, you directed to reply #61, reply #61 (basic dds) specifically said the chip is always runs at 125MHz, acummulator got added every 125MHz...

[c4757p]

We've already established that this chip is not running at 125 MHz. Do the math again for 1 MHz.

no, in your respond, you directed to reply #61, reply #61 (basic dds) specifically said the chip is always runs at 125MHz, acummulator got added every 125MHz...

I was pointing you to the thought processes, not the numbers. I figured you were smart enough to notice the discrepancy and adjust for the different clock frequency.

[Mechatrommer]

We've already established that this chip is not running at 125 MHz. Do the math again for 1 MHz.

no, in your respond, you directed to reply #61, reply #61 (basic dds) specifically said the chip is always runs at 125MHz, acummulator got added every 125MHz...

I was pointing you to the thought processes, not the numbers. I figured you were smart enough to notice the discrepancy and adjust for the different clock frequency.

It's not going to change the clock frequency, Mecha. I feel like you have no idea what you're talking about.

thats only the basic "thought process". sorry if i misinterpret, but i really dont get you. i was "assuming" since its a blackbox, there's no mentioning how to calc at 1MHz, output sample frequency? whats that? its a black box i simply assuming its a "prescaled frequency" (that i believed you denied) from the base xtal. but its not there in the datasheet or elementary description. even if i do the math at 1MHz, i suspect it will still doesnt make any sense, 8 values at 164KHz? with 125MHz base freq, 16 bits everything? thats nonsensical in any imaginable numbers.

[niekvs]

one may argue that the picture posted by hamster is from different dds, but its more robust dss compared to 9850, still output alot less than whats ideal...

Look, you still don't get it. Just because the unfiltered output looks messed up, this doesn't mean that the filtered output will look bad. "Ideal" output is the output that contains all required information to reconstruct the intended sine signal, using the reconstruction filter. In that sense, the 30MHz output of this AD9850 *is ideal*. You just have to follow the datasheet and add proper filtering, after which you will get a "perfect" sine. You can play around with that AD9850 tool on the AD website: set it to 30MHz, don't use a filter at first, and look at the crappy output. Then, click "config filter", set it to a 5th order filter of 42MHz, enable the filter, and watch the output again. Now it's a sine! That's what the filter will do for you. Just because the input to the filter contains frequencies ("images") other than the intended frequency (which makes it look staircased), the filter will remove those images, and what remains is the sine.

Now try setting the filter to 75MHz. Because the first "image" is at 95MHz (125MHz - 30MHz), and because the filter is not that steep, you will see a less than perfect sine. Now it happens that some of these cheap modules apparently were fitted with this wrong 75MHz filter (see http://www.pongrance.com/DDS-9850.html). This explains the less than ideal output at 30MHz. From the very beginning of this thread it was mentioned that the filtering was probably not done well, and people started saying that even with good filtering, this AD9850 cannot produce a good output. This is simply not true.

So again, all this talk about "2 bits output", "4 bits output", "not going over all 1024 values", etc. etc. is not relevant. What's relevant is that enough information is output to reconstruct the intended sine wave after filtering.

[c4757p]

The device will add the frequency tuning word to the phase accumulator at a rate of the clock frequency, and then the phase accumulator goes to the lookup table. That's the basic DDS architecture.

With all values normalized to 1, fc = 1.3 MHz, f = 164 kHz.

f/fc = 0.126154 - this is the frequency tuning word.

Now add this over and over again, at a rate of 1.3 MHz / 769ns:

0.126154,  769ns
0.252308,  1.538462µs
0.378462,  2.307692µs
0.504615,  3.076923µs
0.630769,  3.846154µs
0.756923,  4.615385µs
0.883077,  5.384615µs
0.009231,  6.153846µs (overflow)
0.135386,  6.923077µs
0.261540,  7.692308µs
0.387694,  8.461538µs
0.513848,  9.230769µs
0.640002,  10µs
0.766156,  10.76923µs
0.892310,  11.53846µs
0.018464,  12.30769µs (overflow)

The frequency is approximately 1/6.153846µs or 162.5 kHz. The next time around it'll be a slight bit different because the overflow didn't occur at exactly an integer step, and the average frequency will work out to 164 kHz (write a script to run this for a large number of periods and calculate the frequency at the end, if you like).

No change in clock, no change in DAC resolution. There are eight steps per period, and you'll notice that the values look similar between the two periods I did, but they're not the same.

Edit: By the way, things start to get "interesting" when the set frequency is a nice integer ratio of the clock. Try it, you will lose a bit of effective resolution. There's a reason ADI's DDS sim gives a nice ugly warning if you set it up that way. But that's nothing to do with the DDS chip, that's math. Even this very basic accumulation will exhibit it.

[Mechatrommer]

Look, you still don't get it.

no it is you that dont get it. in fact it is your post that started it that i need to rectify.... and i and you was not talking anything yet about filtering. analog filtering is entirely a different story...

And this whole thing about 4 bits of DAC resolution still makes no sense. The part has a 10 bits DAC. It's not "2 steps, high and low", but 2^10 (1024) possible values

just as other said, can you distinguish a signal 0,1,0,1 and 0,1023,0,1023? no! at most maybe only the larger amplitude if the dds spit out 0,1024,0,1024. but still it is effectively only 1 bit output hi and lo, digitally speaking.

[Skimask]

8 values...it makes sense (somewhat) if the accumulator value is truncated at the top end and sent to the DAC...eg. only the top 3 bits of the DAC are getting changed.  But that doesn't seem to be the case in your particular case, so I don't know WTF...

My original point still stands...you aren't going to get a GOOD DDS Sig Gen for $12 off of chinabay.
Don't know if doing a quicky video on it is gonna do any good.  I loaned out my Tek2465.  All I've got here at the shop that's worth anything is a 2246.  100Mhz bandwidth may or may not be able to show some of the higher frequency content.

[c4757p]

Mecha, read my comment above about what happens when the frequency set is an integer ratio of the clock frequency. Then some of the things you're spewing start to become valid, kinda-sorta-maybe. They don't have to, though, you just avoid that case in practice...

You'd do well to spend more time asking questions than making statements until you've figured this stuff out.

Skimask, stop with this "chinabay" bullshit. DDS is DDS. They all work more or less the same, with different amounts of filtering and different amounts of sample rate overhead.

[Kleinstein]

At a few special frequency setting only some of the tabulated sin values are used. However this is not a disadvantage - after filtering it still results in a clean sine signal. Even if you don't use all possible steps of the DAC, the sine is not getting worse. The important part is how well the required steps are met. Depending on the DAC one may hit a sweep or weak spot of the DAC - thus you likely get the best (especially Phase noise) and worst values at these special frequencies. So spurious signals and noise will be somewhere is the -50 to -60 dB range, not much different from other frequencies.

With a well made filter these DDS chips are really quite powerful - so it's a pity that some of the Chinese Moduls seem to use poor filters. The question is a little why this setup seems to have an upper limit at about 1 MHz. This way of the expected behavior and can't be explained with simple tolerances. Tuning the LC filter so low even starts to get more difficult.

[Mechatrommer]

fc = 1.3 MHz

It's not going to change the clock frequency, Mecha. I feel like you have no idea what you're talking about.

you stated the clock wont change, i was talking about xtal freq of 125MHz got prescaled or something, and you denied it... now you talking about fc = 1.3MHz, i think you are in agreement with me, its just that you have no idea what i was talking about.

[Skimask]

Skimask, stop with this "chinabay" bullshit. DDS is DDS. They all work more or less the same, with different amounts of filtering and different amounts of sample rate overhead.

Yes, DDS is DDS.  I'm there.  Better, worser, etc.  This whole thing started with the notion that this particular DDS module can dump out a decent 30Mhz.

(I'm just here to start shit... )

[c4757p]

fc = 1.3 MHz

It's not going to change the clock frequency, Mecha. I feel like you have no idea what you're talking about.

you stated the clock wont change, i was talking about xtal freq of 125MHz got prescaled or something, and you denied it... now you talking about fc = 1.3MHz, i think you are in agreement with me, its just that you have no idea what i was talking about.

The clock won't change from what's fed into the damn chip, not the clock won't change from what was written. You claimed it'd use prescalers and whatnot. It won't.

[niekvs]

no it is you that dont get it. in fact it is your post that started it that i need to rectify.... and i and you was not talking anything yet about filtering. analog filtering is entirely a different story...

"Entirely a different story"? What exactly are you talking about? What are you trying to prove with your posts so far about the values that the DAC may or may not output? That it's not going to give a good sine? Because - that's exactly what the analog filtering is there for. After this filtering, the sine will be "perfect".

This whole thing started with the notion that this particular DDS module can dump out a decent 30Mhz.

Oh really? Let me refresh your memory:

Even with filtering, point is that those modules generally use a 125Mhz xtal.  30Mhz sine wave with a 125Mhz MCLK will give a guy, what, 4.x bits of DAC resolution, give or take...

As far as filtering goes...  Sure...design all the filters you want.  Try it at 30Mhz and you'll end up with garbage.  Even if you do get a decent sine wave output that's free of distortion, it'll likely only work well within a very narrow set of parameters.

You have to add to the accumulator a number that'll swing the DAC fast enough to give you that 30Mhz output, and it has to be a large number.  As the desired output frequency gets higher, the number of 'steps' in your output drops.

What's this talk about 4 bits? 2 bits? "Even with filtering", etc etc. You stated it's not possible to get a good sine out of this AD9850, "even with filtering". You also made it very clear that you don't know what filtering can do, focusing instead on irrelevant things like "the number of steps", like this makes any difference after filtering...

[Mechatrommer]

With all values normalized to 1, fc = 1.3 MHz, f = 164 kHz.
f/fc = 0.126154 - this is the frequency tuning word.

one question.... where did you get the 1.3MHz?

[Kalvin]

With all values normalized to 1, fc = 1.3 MHz, f = 164 kHz.
f/fc = 0.126154 - this is the frequency tuning word.

one question.... where did you get the 1.3MHz?

See message:
https://www.eevblog.com/forum/projects/30-mhz-ad9850-dds-signal-generator-in-12$/msg679821/#msg679821
"It's actually a AD5541A , a 16-bit DAC, running an output sample frequency of 1,315,789 HZ".

[c4757p]

With all values normalized to 1, fc = 1.3 MHz, f = 164 kHz.
f/fc = 0.126154 - this is the frequency tuning word.

one question.... where did you get the 1.3MHz?

By reading all the posts.

[Mechatrommer]

"Entirely a different story"? What exactly are you talking about? What are you trying to prove with your posts so far about the values that the DAC may or may not output? That it's not going to give a good sine? Because - that's exactly what the analog filtering is there for. After this filtering, the sine will be "perfect".

yes, but because i guess you are too particular about 2 bits or 10 bits arguments. in fact how many bits doesn't really matter if the filtering is robust enough to take care all the sampling rate (stair steps) possibilities. when you were arguing the 10 bits argument, i thought you are saying... at 30MHz, the DDS will have 10 bits output resolutions (1024 varying values or sine phase and all) which is not the case.

otoh, on the analog filtering side, i'm not the expert but eliminating "stairsteps" is straight forward if at one particular "output sampling speed or freq" but it will obscure me for various stairsteps possibilities. what i can see, a good filtering will need to be able to diminish all "stairsteps". if one is not clear what i'm talking about... there is stairsteps at 125MHz sampling speed, ie 8ns of where you can put your feet on. and then there is a stairsteps at 1MHz, ie 1us of where you can put your feet on (the flat horizontal space on the scope), they both have very broad or different harmonics or bw that you are trying to eliminate, that i'm not sure how. if one is to eliminate harmonics at 1MHz output sampling, then it will diminish DDS higher freq output signal (overly low-pass), but if one is to perfectly eliminates harmonics at 30MHz FG output (that is maybe around 125MHz of sampling frequency), the filter wont eliminates stairsteps at lower sampling rate of 1MHz. as i said i'm not the expert and i dont tend to talk about it.

somehow filtering will be related to the "output sampling rate", and thats changing, i believe we are all already in agreement with that and proven in hamsters image.

[c4757p]

Many DDS devices, including full signal generators, just leave the stairsteps at the lower frequencies - they end up being so small they don't have much effect. If I were designing one, I'd investigate a network of switched filters (not switching filters, mind you) to adapt to different frequencies, but it's often decided to be unnecessary.

[Mechatrommer]

With all values normalized to 1, fc = 1.3 MHz, f = 164 kHz.
f/fc = 0.126154 - this is the frequency tuning word.

one question.... where did you get the 1.3MHz?

By reading all the posts.

good! we have made extensive exercise on this matter at... https://www.eevblog.com/forum/chat/review-hantek-dds-3x25-anyone-own-one/ and the comparison... at https://www.eevblog.com/forum/projects/ad9850-module-and-dds3x25-dds-based-fg-compared/

[Kalvin]

One can also run the process backwards:

1. Draw the desired sine wave to a paper.

2. "sample" the sine wave at desired sample rate and record the sine wave's amplitude at each sample instance.**

3. Perform a simple quantization ie. convert the samples to signed integer values.

Now you should have sampled the original sine wave. Let's do the same thing that the DDS is doing in order to get back to the sine wave:

4. Recreate the sampled sine wave by plotting the integer values to the paper.

5. Apply the zero-oder hold which corresponds to a DAC. You should get the familiar stair-case waveform.

6. Apply a reconstruction filter ie. connect the DAC output samples with a smooth curve.* The reconstruction filter will remove all staircase components and the resulting output signal will be a smooth sine wave.

*See also http://en.wikipedia.org/wiki/Zero-order_hold and how the frequency response will have a 3.9224 dB roll-off at Nyquist frequency (Half the sampling frequency). This may be need to be compensated if the output frequency near the Nyquist frequency. One way to compensate this droop is to create a reconstruction filter which will have an inverted frequency response compared to the zero-order hold, thus emphasizing the frequency components near the Nyquist frequency by 3.9224 dB.

** Particularily at lower frequencies it is very easy to see the more quantization steps you have (10 bits vs 4 bits, for example) the better the quantizited signal will match to the original analog signal. The difference between the original signal and the quantizated sample value is called quantization error which will manifest itself as noise at the DDS output signal.

[niekvs]

yes, but because i guess you are too particular about 2 bits or 10 bits arguments. in fact how many bits doesn't really matter if the filtering is robust enough to take care all the sampling rate (stair steps) possibilities. when you were arguing the 10 bits argument, i thought you are saying... at 30MHz, the DDS will have 10 bits output resolutions (1024 varying values or sine phase and all) which is not the case.

I think you may need to read post #34 again. You seem confused about bit depth vs. sampling rate. The DAC is 10 bits. You may only ever see 2 values at a high frequency, but those 2 values can still be any of 1024 (10 bits) values. I said that in post #27. And the two values contain enough information to reproduce the perfect sine(!) after filtering. Something Skimask is still failing to grasp 

[Mechatrommer]

I think you may need to read post #34 again. You seem confused about bit depth vs. sampling rate. The DAC is 10 bits. You may only ever see 2 values at a high frequency, but those 2 values can still be any of 1024 (10 bits) values. I said that in post #27. And the two values contain enough information to reproduce the perfect sine(!) after filtering. Something Skimask is still failing to grasp 

he got sensical points its just he's barking on the wrong tree, and your argument about audiophoolery are valid too.... except the bolded one above... i believe we are talking the same thing, so do i with some of skymask's points... 2 values whatever it is, contain informations, it is agreed. but what information it is, is irrelevant, as long as we have 2 differing points, we are able to construct sine (with proper filtering).

[paulie]

Now it happens that some of these cheap modules apparently were fitted with this wrong 75MHz filter (see http://www.pongrance.com/DDS-9850.html).

I'm convinced this was not a mistake. Chinese hobbyists, being considerably smarter than their average western counterpart, enjoy overclocking these parts which means considerable improvement in upper end performance.

75MHz LPF the chip maker recommends for the AD9851 running at 180MHz.

IIRC OP has mentioned clocking his beyond to 300mhz which might be pushing it but would benefit from even higher cutoff. Personally I have one of the new "corrected" units but would very much like to get the old "defective" ones. Guess I'll have to take matters into my own hands and start dicking with those SMD caps and inductors.

[Mechatrommer]

*See also http://en.wikipedia.org/wiki/Zero-order_hold and how the frequency response will have a 3.9224 dB roll-off at Nyquist frequency (Half the sampling frequency).

assuming one have done this a perfect 0_order_hold for 125MSps on that 9850 output, perfectly tuned for 30MHz signal output. then slap the 9850 to output the 164KHz (1Msps) now what? the T has changed from 8ns to 2us... i guess one have filtered the 8ns out but still leaving 2us - 8ns = 1.992us stairstep visible.

[Kalvin]

*See also http://en.wikipedia.org/wiki/Zero-order_hold and how the frequency response will have a 3.9224 dB roll-off at Nyquist frequency (Half the sampling frequency).

assuming one have done this a perfect 0_order_hold for 125MSps on that 9850 output, perfectly tuned for 30MHz signal output. then slap the 9850 to output the 164KHz (1Msps) now what? the T has changed from 8ns to 2us... i guess one have filtered the 8ns out but still leaving 2us - 8ns = 1.992us stairstep visible.

No. The samples are always output at constant rate of 125MHz (8ns): When the output frequency is 30MHz, the 9850's DAC will output a new sample at every 8ns.  Even if the output frequency is set to 164kHz, the DAC will spit out new sample at every 8ns. The quality of the output signal (how well the output signal matches to the original sampled sine wave) is dependent of how many bits the DAC has. This is particularily obvious at the lower frequencies: For example, if a DAC has only 4 bits (16 output levels), the output cannot represent the original sine wave as well as a DAC with 10 bit output (1024 levels).

[Kedar264]

you all have detail understanding about dds and all about filtering stuff,can you help me by suggesting output circuit to get precise output 

[Mechatrommer]

No. The samples are always output at constant rate of 125MHz (8ns): When the output frequency is 30MHz, the 9850's DAC will output a new sample at every 8ns.  Even if the output frequency is set to 164kHz, the DAC will spit out new sample at every 8ns. The quality of the output signal (how well the output signal matches to the original sampled sine wave) is dependent of how many bits the DAC has. This is particularily obvious at the lower frequencies: For example, if a DAC has only 4 bits (16 output levels), the output cannot represent the original sine wave as well as a DAC with 10 bit output (1024 levels).

here we go again someone read from theory you missed all the fun.

[Kalvin]

No. The samples are always output at constant rate of 125MHz (8ns): When the output frequency is 30MHz, the 9850's DAC will output a new sample at every 8ns.  Even if the output frequency is set to 164kHz, the DAC will spit out new sample at every 8ns. The quality of the output signal (how well the output signal matches to the original sampled sine wave) is dependent of how many bits the DAC has. This is particularily obvious at the lower frequencies: For example, if a DAC has only 4 bits (16 output levels), the output cannot represent the original sine wave as well as a DAC with 10 bit output (1024 levels).

here we go again someone read from theory you missed all the fun.

Oh no, it is not theory. It it obvious even without theory

[hamster_nz]

*See also http://en.wikipedia.org/wiki/Zero-order_hold and how the frequency response will have a 3.9224 dB roll-off at Nyquist frequency (Half the sampling frequency).

assuming one have done this a perfect 0_order_hold for 125MSps on that 9850 output, perfectly tuned for 30MHz signal output. then slap the 9850 to output the 164KHz (1Msps) now what? the T has changed from 8ns to 2us... i guess one have filtered the 8ns out but still leaving 2us - 8ns = 1.992us stairstep visible.

Those screen grabs were just an example of a different DAC output, running at approximately 100th the speed of the DDS chip. Sure,if you put the 30MHz filter on my chip it wouldn't help much, but on the DDS chip it will give a clean signal.

[hamster_nz]

you all have detail understanding about dds and all about filtering stuff,can you help me by suggesting output circuit to get precise output 

This has a design for a completely passive 30Mhz reconstruction filter: http://www.ti.com/lit/an/slaa135/slaa135.pdf and this is an active one: http://pdfserv.maximintegrated.com/en/an/AN3520.pdf.

Due to the sample frequency you should really be using a 62.5MHz reconstruction filter, so you might want to adjust things a bit and check the bandwidth of the parts. Another promising looking part is https://www.hittite.com/content/documents/data_sheet/hmc900lp5.pdf.

But if it was me doing things just for fun, I would look for a dual video op-amp with chip about 60MHz gain/product bandwidth (something like a ADA4898-2), and chain them both when configured for 1x gain. It won't be perfect, but it should be relatively inexpensive and work reasonably OK. It would also be quite fun to experiment with.

[Kleinstein]

The required reconstruction filter of the DDS only depends on the sampling frequency, not the frequency of the output signal. So for 125 MHz sampling the edge can stay a something like 40-50 MHz, depending on how steep it is. This filter will still work smoothing the smaller steps of a 1 MHz sine wave, as the timing is the same. The 62.5 MHz is the frequency where the filter should provide sufficient damping. So half the sampling frequency is the theoretical limit. The practical limit is more like 1/3 of the sampling frequency - so 40 MHz in this case. Even then some adjustment of the amplitude may be helpful. The closer one gets to the the theoretical limit, the better the filter needs to be. If one needs more - choose a faster chip (e.g. AD8951).

In this frequency range the passive Chauer filter is the typical solution - its rather simple and low part count. This type of filter is already on the module. After that some amplification is helpful - for more power and also to isolate the filter from the output impedance. I don't see much advantage in using 2 rather slow OPs - a single higher speed OP (in the 60-300 MHz GBW range) is likely the better choice. Something like 2 OPs in parallel might be needed to get higher power. Finally an attenuator may come handy.

[Mechatrommer]

*See also http://en.wikipedia.org/wiki/Zero-order_hold and how the frequency response will have a 3.9224 dB roll-off at Nyquist frequency (Half the sampling frequency).

assuming one have done this a perfect 0_order_hold for 125MSps on that 9850 output, perfectly tuned for 30MHz signal output. then slap the 9850 to output the 164KHz (1Msps) now what? the T has changed from 8ns to 2us... i guess one have filtered the 8ns out but still leaving 2us - 8ns = 1.992us stairstep visible.

Those screen grabs were just an example of a different DAC output, running at approximately 100th the speed of the DDS chip. Sure,if you put the 30MHz filter on my chip it wouldn't help much, but on the DDS chip it will give a clean signal.

right! this cost me dismantling my whole unit again and probing job. so yeah, this bastard will output at fixed 125MHz or whatever clock you put it in, no prescale or whatever everything is just a simple freq/tuning formula exactly as in datasheet must be few things to happen for a disaster 1) my everlasting memory with AWG DDS mechanism, 2) you put a picture with as little description on it. indeed its 1.3MHz as the "input clock" i cant imagine why someone want to do that? with 5Hz requirement as you stated i believe one still can get with the recommended clock, 0.029Hz step, wait a second... (checking the ad5541 datasheet) its a DAC! not DDS! 3) today must be a bad day for me. what a waste of the whole night someone must be cleaning this thread up...

hence to the OP, you asked what filter? none, because your board already have one on the sina output, that elliptic low pass, otherwise you need to tap sinb and do whatever suggested here for T = 8ns :|

[hamster_nz]

right! this cost me dismantling my whole unit again and probing job. so yeah, this bastard will output at fixed 125MHz or whatever clock you put it in, no prescale or whatever everything is just a simple freq/tuning formula exactly as in datasheet must be few things to happen for a disaster 1) my everlasting memory with AWG DDS mechanism, 2) you put a picture with as little description on it. indeed its 1.3MHz as the "input clock" i cant imagine why someone want to do that? with 5Hz requirement as you stated i believe one still can get with the recommended clock, 0.029Hz step, wait a second... (checking the ad5541 datasheet) its a DAC! not DDS! 3) today must be a bad day for me. what a waste of the whole night someone must be cleaning this thread up...

hence to the OP, you asked what filter? none, because your board already have one on the sina output, that elliptic low pass, otherwise you need to tap sinb and do whatever suggested here for T = 8ns :|

Sorry about that - I thought I was being pretty explicit when I said "Oh, and as an illustration,  here is what the output of a DAC looks like without a reconstruction filter" in the post with the screen grabs.

[Tac Eht Xilef]

you all have detail understanding about dds and all about filtering stuff,can you help me by suggesting output circuit to get precise output 

Sorry OP, it's turned into one of those threads ... 

It's been a while since I looked or thought about it, but I don't think you're going to find a a drop-in example for you to copy. In reality, it's not that easy to solve in a way that makes it worthwhile (e.g. low distortion, stable & flat from near DC->15/20/30MHz, etc) at the price / performance required. There's several reasons cheap DDS-based signal generators tend to top out at 2/5/10 MHz - and that's one of them.

If you Google around, you'll stumble across the circuit shown in this thread - it was originally designed by PA3CKR for his DDS signal generator project, and IIRC is pretty much pieced together straight from TI appnotes. Supposedly it's good for 40MHz, but at those frequencies you're in an area where layout & construction matters just as much as choice of device - it's not a job for an amateur unless they plan on learning a lot.

Personally I'd look at something like the Analog Devices AD600 / AD602 for the basis of the AGC stage - from memory, the datasheet of one or the other has a nice-looking 2-stage AGC example that should be suitable. From there, I'd be looking at high-frequency line driver amps from the likes of TI as an output stage.

[Mechatrommer]

Sorry about that - I thought I was being pretty explicit when I said "Oh, and as an illustration,  here is what the output of a DAC looks like without a reconstruction filter" in the post with the screen grabs.

the output of DDS is a DAC, and sometime in other system, "sampling clock" <> "input" or "base" frequency.

[niekvs]

you all have detail understanding about dds and all about filtering stuff,can you help me by suggesting output circuit to get precise output 

Please also see page 17 of the datasheet, which shows an implementation of a 42MHz low pass filter (the LC filter on the right). ( http://www.mpja.com/download/ad9850.pdf )

The required reconstruction filter of the DDS only depends on the sampling frequency, not the frequency of the output signal.

This is true, if you just make sure to stay under the Nyquist limit (half the sampling freq). However, the location of the "images" does depend on the output frequency (they are located at Freference (125MHz) - Foutput. See also page 9 of the datasheet, so if for example you know you will only use this thing for lower frequency outputs, you can relax the requirements of your filter a bit.

Anyway - glad most here now seem to understand and agree that, while counterintuitive, you don't need to output all those values so that when you connect those dots directly make a pretty sine wave on paper.  Statements like "you will not and cannot possibly use all 10 bits in each 360 degrees of an output sine wave once you get above certain frequencies" are therefore more or less irrelevant. It's indeed "simple math", though not as simple or as intuitive as it may seem at first sight... It's quite magical in fact, when you first "get it", and therefore a pretty interesting subject!

[Kalvin]

Hi all,

I created a simple DDS simulator for LTSpice. The user can vary different DDS parameters like DDS clock, output frequency and number of bits used for DAC and observe how these parameters affect the filtered DDS output signal purity.

When the DDS parameters are set as follows:

- DDS clock frequency = 125.0 MHz.
- DDS output frequency = 30.1 MHz.
- DAC resolution = 10 bits.
- Lookup-table size = 2**12

The result is quite clean sine wave with almost -60dB noise level (see figures a).

When the DDS parameters are set as follows:

- DDS clock frequency = 125.0 MHz.
- DDS output frequency = 30.1 MHz.
- DAC resolution = 4 bits.
- Lookup-table size = 2**8

The result is contains some noise already at -35dB (see figures b).

Pls find the files in the attached zip-file "dds-with-ltspice.zip" (See the last file in the attachments). The Python script "dds.py" will generate DDS DAC output signal which will be imported into simulation file "dds-with-python.asc" containing a 64MHz reconstruction filter.  The program was tested using LTSpice and Python 2.7 running in Linux Mint.

Have fun!

Br, Kalvin

[Kalvin]

Here is the same simulation with the output frequency set to 3.01MHz.

The "c" files was generated with the following parameters:

DDS clock frequency = 125.0 MHz.
DDS output frequency = 3.01 MHz.
DAC resolution = 10 bits.
Lookup-table size = 2**12

The resulting sine-wave has -55dB noise level.

The "d" files was generated with the following parameters:

DDS clock frequency = 125.0 MHz.
DDS output frequency = 3.01 MHz.
DAC resolution = 4 bits.
Lookup-table size = 2**12

The resulting sine-wave has close to -40dB noise level.

[niekvs]

A nice set of tests!

On a related note, here's a excellent document explaining and quantifying the noise resulting from the limited number of bits in the DAC as well as the effect of the truncation of the phase accumulator (in case of the AD9850, the DAC is 10 bits, and the number of bits of phase after truncation is 14). See chapter 4 for the relevant information.

http://www.ieee.li/pdf/essay/dds.pdf

Generally, with the specs of the AD9850, most people probably won't have to worry about these details and should know that it works very well (unless you're not filtering correctly.. And that, if you're getting triangle waves at 30MHz, you're doing something wrong.

[Kalvin]

A nice set of tests!

Thanks! I just wanted to play with LTSpice, do real mixed-signal analysis so that an external program (Python script in this case, see my posting above with an attachment "dds-with-ltspice.zip") creates a file containing a signal to be imported into LTSpice simulation, and the generated signal be used as a stimulus (input to the reconstrcution filter). It was easier than I though. More info about these PWL-files can be found here:
http://www.linear.com/solutions/1815

[paulie]

An Precession Signal generator is very easy and affordable make using an arduino and dds synthesizer (ad9850) .

True. Only took me  few minutes to make use of the Ebay module gathering dust thanks to your excellent instructions. I am really impressed by the rotary encoder method for setting frequency. AD8951 has been ordered so I can use my recent 40mhz GPSDO circuit as input clock for ultra-precise and stable DDS generator. Too bad AD8950 don't have similar input clock ability. Thanks for a great thread.

[vinicius.jlantunes]

Subscribed.

[bingo600]

AD8951 has been ordered so I can use my recent 40mhz GPSDO circuit as input clock for ultra-precise and stable DDS generator.

@paulie

A 40 milli-Hz input would mean quite a different LP filter , even if the 51' can up the clock 6*  to 240mHz 

/Bingo

[miguelvp]

Wonder what happened to paulie, not active since May 30 so unlikely to see your post

[AustinTxBob]

Looks like a fun way to play with the AD9850.  I hooked mine up and it seems ok running at the default 10MHz.  My goal with this is an antenna analyzer for HF frequencies.

[AustinTxBob]

The schematic and the code have a difference.  The schematic lists fqup going to 10 and rest going to 11 but the code has them reversed.

Pretty unusable at higher frequencies as predicted.  Seems like it will work up to 15MHz for my purpose though.

[Chatchai]

The AD9850 good for me  .

[Ranger14]

Do you guys think this is worth building and does it have good enough accuracy??

[retrolefty]

Do you guys think this is worth building and does it have good enough accuracy??

 Well 'good enough' is not a useful unit of measurement. 

However I built a similar device using the AD9850 used as the VFO LO for a ham 7MHz CW receiver. Worked great, heard no distortion, and very stable frequency control. I amplified the output using a MMIC chip to drive a double balanced diode mixer. So lots of capability for very little $, what's not to love?

 

[Mechatrommer]

The AD9850 good for me  .
NewFile6.jpg

congratulation for reading the signal in average mode...

[AustinTxBob]

The AD9850 good for me  .
NewFile6.jpg

congratulation for reading the signal in average mode...

Harsh?  Why not explain what is wrong and why that may not be the best setting?  Us newbies might benefit more from that.

I did get a much cleaner reading on mine by swapping out the ground lead to the spring.  There was another thread talking about this.  Thanks to whomever posted that! (I wish I saved the link.)

[Mechatrommer]

Harsh?  Why not explain what is wrong

no i'm trying to be gentle actually, since most newcomers will get hot when told the truth and they will come with their machine gun theory book. look, my AD9850...

picture 1) very nice!
picture 2) so so
picture 3) well?

bear in mind this is sampled 25 points per cycle (40MHz @ 1GSps)
picture 4) how a theoritical 25pts sine should looks like.

conclusion: "average" will closely resemble perfect sine. "single capture" (picture 3) is the truth. if we want talk sweet and sugar, we show "average", if we want to talk the truth grain and salt, show "single capture", "average" is nice, but not truth. and lastly... use 1X attenuation 50 ohm Z coax with 50 ohm termination at the scope end when testing, thats the de-facto standard way... google it its too long, fwiw..

picture 5) when superimposed theory and the truth... fwiw..

[AustinTxBob]

and lastly... use 1X attenuation 50 ohm Z coax with 50 ohm termination at the scope end when testing, thats the de-facto standard way... google it its too long, fwiw..

Googling that now.  Thanks!  As you can see from the pics I posted, I took a single instead of the OP's average.  Also I was just probing directly on the board with no termination. 

I'm putting it into an antenna analyzer right now so we'll see what it looks like when it is seeing 50 ohms.