Hi all,
I have a question regarding production yield / defects due to differences in line width in 300+ pin BGA devices.
I got the design guide from this (Chinese) manufacturer but it has some things in it that make me doubt
that they are correct design practices.
Around 50 pins of this chip are for different power pins and gnd pins. Most of these are concentrated in the middle.
The design guide states that the line width for these should be >= 10 mil.
All other signals are 4 mil (or 3.8 mil for usb ...).
Would this difference in line width cause higher rates of fault during production ? (this is 1-10K production)
Practice according to design guide:
My thinking:
The trace length is:
16.69 mil (0.424mm).
4mil trace resistance: 1.75m ohm
10mil trace resistance 0.7m ohm
There is a full GND plane on L2.
So there is actual (measurable) difference there. But how much resistance would a via add ?
Since than It can be seen if this is a significant part or not.
I don't know what a normal plating thickness is. Any Ideas?
http://circuitcalculator.com/wordpress/2006/03/12/pcb-via-calculator/I'm just trying to figure out what the best design practice is.
Thanks