Author Topic: 396 pin BGA , question regarding yield due to differences in line width  (Read 1423 times)

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Offline SpikeeTopic starter

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Hi all,

I have a question regarding production yield / defects due to differences in line width in 300+ pin BGA devices.

I got the design guide from this (Chinese) manufacturer but it has some things in it that make me doubt
that they are correct design practices.

Around 50 pins of this chip are for different power pins and gnd pins. Most of these are concentrated in the middle.
The design guide states that the line width for these should be >= 10 mil.
All other signals are 4 mil (or 3.8 mil for usb ...).

Would this difference in line width cause higher rates of fault during production ? (this is 1-10K production)

Practice according to design guide:


My thinking:


The trace length is:
16.69 mil (0.424mm).
4mil trace resistance: 1.75m ohm
10mil trace resistance 0.7m ohm
There is a full GND plane on L2.
So there is actual (measurable) difference there. But how much resistance would a via add ?
Since than It can be seen if this is a significant part or not.

I don't know what a normal plating thickness is. Any Ideas?

http://circuitcalculator.com/wordpress/2006/03/12/pcb-via-calculator/

I'm just trying to figure out what the best design practice is.

Thanks
« Last Edit: October 13, 2016, 11:34:45 am by Spikee »
Freelance electronics design service, Small batch assembly, Firmware / WEB / APP development. In Shenzhen China
 

Offline DutchGert

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Re: 396 pin BGA , question regarding yield due to differences in line width
« Reply #1 on: October 14, 2016, 04:31:16 pm »
The first one for sure, you can even make the trace as wide as the BGA pad.

What you want for power en gnd is low inductance.The difference in resistance between the two does not matter, the inductance does.... 

As long as you have a good oven to reflow the BGA there should not be any problems. In theory a small trace acts as a thermal relieve but in a good over that preheats the board its no problem and you should go for good power integrity

ps. you are Dutch, draw and design in mm, not the mil/inch rubbish ;)

« Last Edit: October 14, 2016, 04:35:56 pm by DutchGert »
 

Offline DutchGert

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Re: 396 pin BGA , question regarding yield due to differences in line width
« Reply #2 on: October 14, 2016, 04:38:46 pm »
BTW, a TH via with a 0.2mm end size and a 0.4mm pad is not good design practice (and not IPC compliant). Make that via pad 0.6mm if you can or at least  0.45 or bigger.

Read the design guidelines of the board manufacturer. Some examples:

http://www.eurocircuits.com/PCB-design-guidelines
http://www.we-online.com/web/en/index.php/show/media/04_leiterplatte/2011_2/relaunch/produkte_5/012012_Basic_Design_Guide.pdf
« Last Edit: October 14, 2016, 04:43:00 pm by DutchGert »
 


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