It can be done without an FPGA, but the circuit will be huge if done without an ic dedicated for that purpose:
Before adding more lines you need to make room for them. That means you need to store some lines in memory, because you are adding 60 lines at the top, therefore your output image starts later. That's why there is no simple solution using some discrete logic.
Most display controllers designd for LCD monitors typically scale the image, but can probably also configured for placing the unscaled image in centre of the output image if there is enough memory.
The main problem with using such a one chip solutions is, they are designed for high volume products. Unless you are going to build many thousand devices, it is nearly impossible to get those parts from official distributors.
With a bit of experience in FPGAs it can probably done in one or a couple of days, because FPGAs have everything needed for this: Logic, PLLs for generating the higher output clock and memory for storing a small part of the image.
If you aren't willing or have no time for learn FPGAs, find somebody who can do this for you. Even if you pay somebody for doing this, it will still be the most economical solution.