Author Topic: 4:2:2 YCbCr video -- Centering lower-res on a higher-res display?  (Read 1048 times)

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Offline smoothVTerTopic starter

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I am in search of a method to process a 16-bit YCbCr video bitstream at 640x480 resolution and center it on a panel with a native 800 x 600 resolution.   

The panel itself has some built-in adjustability for image centering but only for +/- 10 pixels in either direction.     I know conceptually that in order to achieve this centering, the 640x480 bitstream requires processing and timing changes to the HSYNC/VSYNC signals, as well as 'adding in' blank pixels to the left/right/top/bottom of the lower resolution image and making adjustments in timing to account for these extra blank pixels.

Many people say to do this in an FPGA ... but is there a simpler solution?  I have zero experience in FPGA's and the learning curve seems steep.   In my search for non-FPGA IC's I find a dizzying selection of video processing / decoding chips out there that have an overabundance of functionality ( and power consumption ) which my application does not need.  I already have a decoded and formatted YCbCr video stream, so I don't need any kind of decoder/encoder IC.   I just need some way of generating blank pixels and timing changes to HSYNC/VSYNC.

  • Is there a non-FPGA, one-chip solution out there to achieve this video centering?
  • Any other recommendations, or perhaps I am thinking about this the wrong way?








 

Offline bktemp

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Re: 4:2:2 YCbCr video -- Centering lower-res on a higher-res display?
« Reply #1 on: April 29, 2017, 03:38:03 pm »
It can be done without an FPGA, but the circuit will be huge if done without an ic dedicated for that purpose:
Before adding more lines you need to make room for them. That means you need to store some lines in memory, because you are adding 60 lines at the top, therefore your output image starts later. That's why there is no simple solution using some discrete logic.
Most display controllers designd for LCD monitors typically scale the image, but can probably also configured for placing the unscaled image in centre of the output image if there is enough memory.
The main problem with using such a one chip solutions is, they are designed for high volume products. Unless you are going to build many thousand devices, it is nearly impossible to get those parts from official distributors.

With a bit of experience in FPGAs it can probably done in one or a couple of days, because FPGAs have everything needed for this: Logic, PLLs for generating the higher output clock and memory for storing a small part of the image.
If you aren't willing or have no time for learn FPGAs, find somebody who can do this for you. Even if you pay somebody for doing this, it will still be the most economical solution.
 
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