An ECL comparator pulse stretcher

[Fulcrum]

Good day!
I am Fulcrum, a new member here at the EEVblog. I've been following Dave Jones' youtube channel for some years, and have learned lots, but now I need a bit of help!

So at the core of this problem lies the ADCMP553, a low voltage positive emitter coupled logic (LVPECL) comparator. I have made pulse stretchers from comparators before, following this handy guide. Works a charm. However with the ADCMP553, it's not so trivial.

First of all, I am unsure of how the latch inputs work on an ECL device. The datasheet says (page 3) that the latch enable inputs will draw anything from -150µA to 150µA. I find this hard to understand. Is it simply not possible to say if the inputs will source or sink current?

Now, what I thought I could do, is get rid of the discharge resistor R1 in the circuit diagram in the article I linked. The datasheet tells me that the latch inputs have internal pullup resistors, and that they source/sink 150µA(Or do they?). So the latch inputs will only latch the output as long as they have some current to draw/sink from/to the capacitors. When the capacitors have been depleted, the latch inputs will technically be floating. The datasheet tells me that floating latch inputs default to their unlatched state. All well and good! So I will simply have to choose capacitor values that give me a latched comparator for the time I need, which is about 50ns. Another way to think of it is that the capacitor couples the AC components of the comparator output to the latch input, while blocking DC.

However, I don't like building circuits without performing simulations to give me confidence that they will actually work as intended. And since there are no simulation models available for the ADCMP553, that's not so easy! Therefore I would very much like to hear your opinions on this. And I can't choose the obvious, easy solution, of replacing the ADCMP553 with a different comparator. The pulses I am going to detect are ~1ns long, and most non-ECL comparators have minimum pulse widths of 2-3ns at best.

[azer]

I see there is a spice model for its brethren ADCMP551 here http://www.analog-innovations.com/subcircuits.html. Not an official one, but it might suffice.

[Fulcrum]

Oh, that is interesting. I eventually found a design that should work for me, but it ended up being rather complicated. It's good to have a spice model in hand either way, in case I stumble upon some strange behavior. Thanks a lot!

[Marco]

The pulses I am going to detect are ~1ns long, and most non-ECL comparators have minimum pulse widths of 2-3ns at best.

Bit late to this party ...you could probably just have used a schottky diode detector with a standard logic monostable.

[tggzzz]

It's good to have a spice model in hand either way, in case I stumble upon some strange behavior.

You always need to assess what any model (Spice or otherwise) does and does not describe. Many Spice macromodels only show gross normal behaviour, and don't show any of the nasty behaviour, e.g. associated with being used out of spec.

Several decades ago I was asked to quote for some logic models, but there were no acceptance criteria. The client was a salesman that had to tick a checkbox before he could sell something. I declined to quote.

[Fulcrum]

The pulses I am going to detect are ~1ns long, and most non-ECL comparators have minimum pulse widths of 2-3ns at best.

Bit late to this party ...you could probably just have used a schottky diode detector with a standard logic monostable.

I don't have experience with schottky diode detectors, but I doubt it would work. I need to be able to set the comparator level.

[Marco]

It's simply a diode peak detector made with a (rf) Schottky diode. So you use an emitter follower to buffer the signal to feed the peak detector with ~100 pF sampling capacitor (that's why you need the buffer, to get a useful time constant with the relatively large capacitance). Then use a slow comparator afterwards.

Or you can buy something similar as an IC, such as LTC5536/LTC5564.

[Fulcrum]

It's simply a diode peak detector made with a (rf) Schottky diode. So you use an emitter follower to buffer the signal to feed the peak detector with ~100 pF sampling capacitor (that's why you need the buffer, to get a useful time constant with the relatively large capacitance). Then use a slow comparator afterwards.

Or you can buy something similar as an IC, such as LTC5536/LTC5564.

What you are talking about is a peak extender, yes? I thought of that. The problem is that the signals I am trying to detect can be very small, much less than the voltage drop over the diode. And the discharge time of the sampling capacitor would greatly diminish the rate of which I can detect the signals.

[Marco]

Oh, you can in theory amplify ... but yeah, it's easier to just use the ultrafast comparator in that case.

Although it's really late now I still want to comment a bit on the original post by the way.

First of all, I am unsure of how the latch inputs work on an ECL device. The datasheet says (page 3) that the latch enable inputs will draw anything from -150µA to 150µA. I find this hard to understand. Is it simply not possible to say if the inputs will source or sink current?

I assume because the spec is for both inputs, they are biased to different voltages so for a given PECL input one of them will be positive and the other negative. Of course it would make more sense to simply give a single entry "Latch enable inputs currents at valid PECL levels" OR give 2 for each input separately. It's not important though ... under normal circumstances you should be voltage driving the inputs with low source impedance making this tiny current mostly irrelevant (for example, 50 Ohms times 150 uA is bugger all).

Now, what I thought I could do, is get rid of the discharge resistor R1 in the circuit diagram in the article I linked.

The latch enable inputs in normal driven operation are supposed to operate in a limited voltage range. While left floating (with the comparator tracking) they are not. The operation of the comparator when going between these two states is not specced, it might be dog slow for instance. It's better to just design the circuit so the latch enable inputs are driven by valid PECL inputs. You might be able to do it with a bunch of resistors, capacitors and diodes ... but some extra logic ICs would be easier.

So the latch inputs will only latch the output as long as they have some current to draw/sink from/to the capacitors.

Nope, that's not how it works. The input currents are what they are when the inputs are driven by PECL signals. They are a result, not a cause. Basically there are three valid states for the inputs, PECL high, PECL low and unconnected (transition between PECL high and low is obviously allowed). The input currents are an artifact of implementation which you should not be relying on.

[Fulcrum]

Now, what I thought I could do, is get rid of the discharge resistor R1 in the circuit diagram in the article I linked.

The latch enable inputs in normal driven operation are supposed to operate in a limited voltage range. While left floating (with the comparator tracking) they are not. The operation of the comparator when going between these two states is not specced, it might be dog slow for instance. It's better to just design the circuit so the latch enable inputs are driven by valid PECL inputs. You might be able to do it with a bunch of resistors, capacitors and diodes ... but some extra logic ICs would be easier.

Thanks a lot for all your input. It's really helping me clear up some confusion.
I didn't even consider the fact that the transition for latched to unlatched might take a long time.

[Marco]

Well, it's specced as fast IF the latch enable is driven purely by PECL ...

It's simply unspecced if you try to go from floating to PECL. Some of the transistors might be saturated while floating, thus making a transition away from that operating mode slow. I'm not saying it's likely, but it's often a good idea to just use the IC as intended when possible.