Another electronic DC load - 60V / 20A / 300W

[electricar]

Hey folks,

I would like to present you the current status of my electronic DC load and would be very grateful if you could have a look at the schematic and tell me what you are thinking about this design.

My rough requirements were:

•   Max. input voltage: 60V
•   Max. input current: 20A
•   Max. power: 300W
•   DUT input isolated from digital control
•   CC/CV/CR/CP mode
•   Reverse polarity protected
•   External setting input
•   External trigger input
•   External sensing inputs
•   Slew rate control
•   Touch display control
•   Powered from mains

My project is splitted into three parts, the digital, analog and 230V part. I'm splitting this because I'm doing my first design in Altium and it could easily be possible to screw some things up in the first revision. Not only regarding the design but also regarding the Altium toolchain. Also the analog part will be a quite large PCB (20x6cm) (I don't need so much space for the components, but the heatsink is quite large) and I don't want to put everything on one board because newer revisions would be very expensive looking at PCB costs.

Digital part:
This part is equipped with the MCU (Arduino Due), Isolation (SI86xx), 3,5" Nextion touch display, watchdog, EEPROM, buzzer, RTC, rotary encoder and off course the power supply for the digital part.
The schematic is mostly finished, but I decided to finish the analog part first, test it and afterwards go on with the digital part.
The digital board gets and sends information about voltage, current and some other things through an isolated SPI (Si8651).

230V part:
This part exists only of a transformer with the bridge rectifier and bulk caps. 2x +15V are generated on this board. The analog and digital part are powered isolated from each other from this board.
I have not started with the design of this board yet. It will be the last one because I can test the digital and analog part with my power supply which delivers also several isolated outputs.

Analog part:
This part is equipped with its power supply, the DUT input, sense measurement, AUX setting, external trigger, slew rate control, two identical current control circuits, ADCs, DAC, reference voltage, SPI IO expander and two LM35s. The schematic of this part is in the attachment.
I’m quite unsure about the input snubber network. After some simulations I came along with very big resistors and capacitors. Is this really necessary or am I overengineering here?
Also my current solution for the slew rate control is changing the time constant of a RC filter by adding capacitors in parallel through the analog switchs U6&U7.
I'm not going to get a nice straight rising and falling edge because I'm not charging the capacitors with constant current. The edges will look like normal charging curves, but that is sufficient for me.

Your feedback is highly appreciated!
Thank you very much in advance!

Kind regards

[Kleinstein]

The MOSFETs don't look like they have a suitable SOA. They might blow up due to thermal instability at more than 40 V and 1 A. At least I have quite some doubt the shown SOA curve is real - they shown no sign of thermal instability in a modern 100 V MOSFET that should have one. So likely this is just the curve representing P_tot.

I very much doubt the constant voltage mode would be stable. There is quite a lot of filtering at the voltage reading inputs and the final control loop OPs are rather fast. This is calling for oscillation, even with a well behaved load.

[electricar]

Hi Kleinstein,
thank you for your feedback!
Where are you getting the relevant information about the thermal instability from? Is it “Figure 2. Transfer Characteristics”?
When I look at the “standard” electronic load FET IRFP250N, I cannot see a much better behavior or am I misinterpreting things here?
Which FET would you rather recommend?

About the CV mode: What would be the right way to get rid of the possibility of oscillation?
Not to fit C22, C25, C15, C21? Get a slower OP? Or both? Or is another implementation of the CV mode needed for a stable load?

Thank you very much in advance!

Kind regards

[Kleinstein]

Analog (that is constant high P_tot) operation of MOSFETs is an often discussed problem. The problem with the proposed FET and some other modern FETs is that the SOA curve in the DS has a high probability to be wrong.  Usually a MOSFET nees a rather high ration of P_tot to trans-conductance, and this value is not very good for this FET. The IRFP250 is at 190 W and 12 A/V (min), maybe 15 A/V typical.
The FQA70N10 is at 214 W and 48 A/V (typical). So the ratio is only about 1/3.  So it is rather unlikely this FET will not show thermal instability at some voltage. It is well known that some SOA curves are just wrong missing this point, as those modern FETs are not intended for linear operation. This sometimes happen if they use formulas to derive the SOA curve from the thermal impedance curves. So if you find the thermal impedance curve and no break in the SOA curve there is a good reason to not trust that MOSFET for linear operation unless it is explicitly mentioned in the DS  (some versions of the IRFP250 DS do that).

So the IRFP250 might be a good choice.

For the voltage feedback, removing the capacitors would be a first step. For critical loads one would even need a kind of partial high pass characteristic instead. It would also help a little to simplify the difference amplifiers to just one OP. The final OP doing regulation would also need a kind of PI type feedback. The probably better alternative is to leave the rather fast current loops in place and add a relatively slow operating "regulator" stage with an OP with RC in feedback that controls the current set values.

The slew rate stage is working as a simple RC filter, not as a slew rate limiter. A simple version would use software control if the DAC and only a little filtering - a true analog implementation is also possible, more like adjusting external compensation of an OP that supports it (e.g. LM301).

So far I have not found a constant resistance mode circuit - this would normally use a signal derived from the voltage to control the reference input of the current setting DAC.

p.s. With the CV mode it is still a good idea to have some current limiting in place.

[electricar]

Thank you again for your feedback Kleinstein! I'm glad that there is so much to learn in EE!

I’ll have to get deeper into forward transconductance and thermal instability in linear operation but I think I got your point. I will stick to the IRFP250N for now as it is also used in many loads and should be good for the beginning.

Jay_Diddy_B has also some good information on this topic:
https://www.eevblog.com/forum/projects/did-i-forget-anything-constant-current-load/msg170808/#msg170808

Concerning the voltage feedback:
I implemented the differential opamps to get a higher precision of the voltage reading on the input voltage because of the voltage drop on the reverse polarity FET Q1.
I played a little bit in LTspice and came up with this solution:

Did you mean something like this?

Also keeping the cap between the output and negative input of the current controlling opamps in CV mode too, improves the behavior (U19B moved to the right side of C42):


Concerning the slew rate limiter:
My plan was to try it in SW with the DAC too, but I have no experience how well this is going to work. That’s why added the different caps for the RC filter to play around as I’m not sure how to implement the analog solution with the fast precision opamps which do not have the compensation feature.
Off course it would be a nice feature for this electronic load to have a real slew rate limiter, but as for now it is not my biggest concern. If someone has a nice circuit for this I will gladly implement it

Concerning the CR mode:
Yes, I didn’t find any too. That’s why I’m going to test it in SW.

Concerning the current limiting in CV mode:
Thank you for this hint! I have totally forgotten this.
I was thinking about a summing amplifier which sums up the input “currents” and goes into a negative input of an opamp. The positive input is fed by my currently unused third DAC channel. The output is then connected through a diode to the CV mode voltage “VDUT”. Something like this:


But this is oscillating a lot. Is this at least the right direction to go or would you solve this differently?

[nctnico]

You could look at the schematics in a service manual for an Agilent DC load. For example the N3305A (120V/50A) or N3306A (60V/120A).

[Kleinstein]

There is no advantage in having the extra buffer amplifiers for current sensing. They only add delay and costs. One can directly use the differential amplifier with a gain of about 1/15.

The RC in the feedback of the extra OP only makes sense if there is also a resistor to GND or the set value for the voltage. Switching between CC and CV mode still does not look like it works. In CV mode, there should be only one common controlling amplifier, so more like the one in the first picture.

The logical way would be have the individual current loops still active and this way make sure current sharing is working. The CV part would control the current set point. Limiting the current in CV mode would than be something like a clamp circuit. One might use the same configuration in CC mode too - just set the voltage very high, so that current is set by the clamp, not the CV part.

[electricar]

You could look at the schematics in a service manual for an Agilent DC load. For example the N3305A (120V/50A) or N3306A (60V/120A).

Hello nctnico,

do you have one of those? I can only find the user manual in which the schematic is not present and the data sheet:
http://cp.literature.agilent.com/litweb/pdf/5980-0232E.pdf
in which they write: "Note: no service manual available for this product"

Kind regards

[tszaboo]

Your FET current regulation has also problems. Max current is 20A, you will run it through 20 pieces of 1 Ohm 1W resistors. So each resistor is dissipating a watt. The issue, while they are rated for a watt, they are rated, such the ambient temperature is low, you need to de-rate them. You will have 20W dissipation into your PCB that is bad also.
I suggest getting some specialized metal element current sense resistors, in the range of ~50mOhm, and increase the gain. Maybe a wirewound through hole would also work, but I dont like those, because of the tolerances mean differences in the FET current.
About the FETs... I'm almost sure, you are outside the FETs FBSOA (forward bias safe operating area). Since this is very rarely specified, I would go with a FET which has this, even though they are more expensive. Or grossly de-rate the FET. Basically most part at the "high voltage, few amps, DC" part is the thermal runaway part.

[Kleinstein]

I noticed the max4425x is a chopper stabilized OP and thus has a relatively long time for recovery from overload. This can be a big problem for some of the regulator type circuits.
It might be thus a good idea to use 2 OPs for the current loop: the AZ type OP to amplify the voltage over the shunt and a second non AZ OP for the regulation loop.

It can be a good idea to check for saturation in the CC mode and thus add an other protections against voltage below something like 1 V. Otherwise the FETs might be controlled all the way on when no power source is connected and than allow for a very large inrush current when a source is connected.

The constant voltage mode can be kind of tricky, as this somewhat similar to an LDO voltage regulator, but with essentially no output capacitor. So don't expect a really good regulation or really low impedance.

[electricar]

Wow thank you guys for all your feedback, quite some things to work on!

There is no advantage in having the extra buffer amplifiers for current sensing. They only add delay and costs. One can directly use the differential amplifier with a gain of about 1/15.

Which opamp do you mean? U8B/D in the schematic? They are only used for the ADC, not for the control loop.

Your FET current regulation has also problems. Max current is 20A, you will run it through 20 pieces of 1 Ohm 1W resistors. So each resistor is dissipating a watt. The issue, while they are rated for a watt, they are rated, such the ambient temperature is low, you need to de-rate them. You will have 20W dissipation into your PCB that is bad also.
I suggest getting some specialized metal element current sense resistors, in the range of ~50mOhm, and increase the gain. Maybe a wirewound through hole would also work, but I dont like those, because of the tolerances mean differences in the FET current.
About the FETs... I'm almost sure, you are outside the FETs FBSOA (forward bias safe operating area). Since this is very rarely specified, I would go with a FET which has this, even though they are more expensive. Or grossly de-rate the FET. Basically most part at the "high voltage, few amps, DC" part is the thermal runaway part.

I was planning to use these resistors:
http://www.isabellenhuette.de/fileadmin/content/praezisions-leistungswiderstaende/SMS.PDF
but you are right. Although the power dissipation for the resistors would be fine, the power dissipation on the PCB would be quite high. I’m moving down to 0,05-0,075R.

I did some derating on the FQA70N10 which was ok until I heard about the missing thermal runaway in the datasheet. I’ll have to do it off course for the next FET. I found some FETs with the DC and thermal runaway in their datasheets, but most of them are for 50-60V. Can somebody suggest a FET which would be good for linear operation combined with the requirements?

The only problem I get with those smaller shunt values is the smaller voltage which is fed back to the negative input of the current controlling opamp, but my DAC voltaga is still 0-2,5V. I guess that is what Kleinstein is talking about concerning the two opamps (the AZ and no AZ type) to amplify the shunt voltage.
That would be another configuration than now, as I am currently feeding the voltage across the shunt directly to the current controlling opamp. The differential opamp is only for the ADC.
I saw that kind of control loop in the schematic of the HP 6060B. But they are using an inverting configuration. Does the inverting configuration have advantages over the non-inverting in a design like this?

I noticed the max4425x is a chopper stabilized OP and thus has a relatively long time for recovery from overload. This can be a big problem for some of the regulator type circuits.
It might be thus a good idea to use 2 OPs for the current loop: the AZ type OP to amplify the voltage over the shunt and a second non AZ OP for the regulation loop.

It can be a good idea to check for saturation in the CC mode and thus add an other protections against voltage below something like 1 V. Otherwise the FETs might be controlled all the way on when no power source is connected and than allow for a very large inrush current when a source is connected.

The constant voltage mode can be kind of tricky, as this somewhat similar to an LDO voltage regulator, but with essentially no output capacitor. So don't expect a really good regulation or really low impedance.

Yes, this is an important protection feature! It could be added relatively easy in HW with e.g. the classic bjt current limit circuit around the shunt or perhaps also in SW, but I think that would be too slow. I’ll try that out. Do you know a better/safer implementation?
And yes, the CV mode is really tricky! Mostly because I don’t really know how to simulate this and my knowledge about opamp stability is not that advanced. That’s one thing I wanted to become better through this project.

[tszaboo]

You can choose a FET which is researched for you. HP/Agilent manuals are good source for this, and some of Dave's teardown video has electronic loads. The other option is to go with fets which are designed to linear. IXYS is a good manufacturer for that. Lots of BIG FETs with low Tjc and big surface.

The isabellenhütte resistors are going to be excellent. Only, the architecture you are suggesting is good for 1-2A/FET, at 5A the dissipation and the loss of usable voltage is too big. Also, ground currents will make a big inbalance, since your setpoint and feedback is both ground referenced.

Oh yes, and CV mode can be really really tricky. I had the chance to make a circuit behave well both in CC and CV mode, different ranges (charge, load, 50mA-50A), tricky loads (batteries with 2mOhm internal resistance), very fast circuit. It was a month or two to do all the testing and hacking until the circuit behaved well everywhere, and I had to get my university book for control theory the first time.

[Kleinstein]

Using a smaller shunt resistance is likely better. Also one should use just one resistor - several in parallel does not work well with 4 wire sensing. Having amplification of the current sense signal before the loop helps in two ways: it can reduce problems with ground bounce and the OP used for the regulator does not need to be an AZ type. The amplification is already there for ADC anyway.

I mixed up voltage and current sensing: so no need for the buffers in voltage sensing of cause. The current sensing actually would like the extra amplification.

For getting better stability in the CV mode, it might be an idea to add a extra output snubber, or even output capacitance with an relay.

Simulation of the control loop is a good idea - the drawing suggest LTSpice is already used.

For the MOSFETs, the IRFP250 does not look that bad. Just don't use too much power / current per FET. So with 60 V maximum voltage the limit is more like 1-2 A per FET. It could be more at lower voltage. Getting a good fail-safe protection is tricky, as with some sources with a lot of inductance it might not be safe to turn off fast.

[electricar]

Hey folks,

sorry for my late reply but I was very busy lately but I finally found some spare time again

You can choose a FET which is researched for you. HP/Agilent manuals are good source for this, and some of Dave's teardown video has electronic loads. The other option is to go with fets which are designed to linear. IXYS is a good manufacturer for that. Lots of BIG FETs with low Tjc and big surface.

Yeah, that’s why I will give the IRFP250N a try. It is in quite a lot loads from BK Precision.
The HP 6060B has eight IRF540.

Using a smaller shunt resistance is likely better. Also one should use just one resistor - several in parallel does not work well with 4 wire sensing. Having amplification of the current sense signal before the loop helps in two ways: it can reduce problems with ground bounce and the OP used for the regulator does not need to be an AZ type. The amplification is already there for ADC anyway.

Thank you for your input, I’ll implement this. I was thinking about the OP27 as non AZ type. What do you think?

For getting better stability in the CV mode, it might be an idea to add a extra output snubber, or even output capacitance with an relay.

Where exactly do you suggest to add a snubber or a capacitor? Can you please spot a RefDes in the schematic?

For the MOSFETs, the IRFP250 does not look that bad. Just don't use too much power / current per FET. So with 60 V maximum voltage the limit is more like 1-2 A per FET. It could be more at lower voltage. Getting a good fail-safe protection is tricky, as with some sources with a lot of inductance it might not be safe to turn off fast.

Yes, that’s why I want to limit the power to 250-300W. So at 300W and 60V that would be 5A in total, what yields to 1,25A per FET what could be ok.

My main problem right now is that after adding the differential amplifier in the feedback loop of the current controlling opamp, my circuit is oscillating with VDUT > 4V.
This also happened only after simulating all four load FETs simultaneously.
I added a lot of components which I found in different electronic load designs to get rid of the oscillations but I’m not able to get this circuit stable with the differential amplifier in the feedback loop and I’m not sure if I’m looking here at some spice-model issues or if this circuit is unstable indeed.

If I reduce Rf to 10k the circuit gets very stable for this scenario but I cannot reach 5A per FET because Rf and Rout form a 0,5 factor voltage divider.

It would very helpful if someone who is familiar with opamp stability and LTspice models could have a look.
The simulation attached has fitted all components, just to make it easier to change and delete not needed components.

Thank you very much in advance!

Kind regards

[Kleinstein]

The current controlling stages usually should work without R_snub, C_snub and Rf.
If needed at all Rf2 should be about equal to Rout / 10 (not less than about 200 Ohms) and Cf2 about 100 times Cf.
R_gate likely needs to be a little larger - so that it effectively isolates the gate capacitance from the OPs output. If a really fast response is needed (e.g. good CV mode) one might need a kind of emitter follower driver for the gate.

For adjustment I would prefer an AC simulation to make sure the output admittance is well behaved (less than 90 deg. phase shift). One may have to increase C5 to get stability and maybe adjust R20. If a large C5 gets a problem one might be able switch between values as the number of active output stages is reduced for small currents.

The more important simulation would be transients on the voltage source, not steps at the set current. A fast response to steps in the set current is nice to have - a gentle behavior in voltage steps is a must.

The OP27 is well good enough - one might well get away with a lower quality one. But this is usually more like a thing to decide later.


Protection can be a rather tricks thing with a electronic load: when the power limit is approached for some reason, there are two possible ways to reduce the power: higher current to reduce the voltage or lower current. It depends on the power source connected. With an inductive source, turning off the current would result in an over-voltage spike. So one might need some extra transient protection for this.  It might need a kind of switch to chose the type of protection by the user and it might well need quite some reserve for transient power. One should definitely have fuses, just in case.

[electricar]

Hi Kleinstein,

thank you for your feedback! It looks like this is going to be a long trip for me

Yes, I thought about AC analysis but I don't know how to implement it for four channels because I have to add the AC source in the feedback loop of the control opamp, right? And I got four of them.

So first let's start with the AC analysis of one channel. I attached the AC simulation for one channel with your suggestions and some adaptions.
I saw the AC analysis of Jay_Diddy_B's electronic load. He modeled the opamp instead of using it's spice model. Is there a disadvantage when using the spice model?
Also his simulation has only one opamp. Is this also an important factor?
Perhaps that is the reason why my phase hardly goes below 43°? I read about to target a gain margin >10dB. If my phase doesn't reach 0° I will get a gain margin >10dB. So this should be ok? Also too much gain margin is not good, but how much is too much?

I'm still not sure if my attached method for the AC analysis is right, because if I do the "DC" analysis, this circuit is oscillating extremely

Kind regards

[Kleinstein]

Using spice OP models is OK - it should work with OPs. The simulation might take slightly longer this way, but not a big deal today. he 2 OP circuit is a little more complicated and thus has a few more chances to oscillate, but also more possible adjustments. The OP solution might be faster, but it is difficult to get best precision.

The frequency range is just to small to see the phase going down. You get phase 0 at about 20 MHz.

However the simulation is running to test 0 current - so the MOSFET is essentially not active. One needs to simulate at more realistic current. At 2 A one can see it is unstable.

It is Ok to use just one channel. 4 in parallel should work the same if the RC at the output is also adjusted.

[electricar]

Hi Kleinstein,

thank you for your feedback. Unfortunately I’m currently not able to get the control loop stable with an additional opamp in the feedback loop with my “chosen” opamps.
With the single opamp solution the stability was relatively easy to achieve, but as you said already, it’s difficult to get good precision.





It’s really interesting that when I use the really high speed opamps (LT1193 and L1220) from this article:

http://www.edn.com/design/analog/4368416/Design-a-100A-active-load-to-test-power-supplies

the load seems very stable in the DC analysis (with a load step from 1A to 5A with different VDUTs (except for 2,5V, there is a little overshoot)).



But in the AC analysis with e.g. an ISET voltage of 1,5V and VDUT of 6V the bode plot doesn’t look like a stable one…



I read about a rule of thumb that the GBW of the current sense opmap has to be ~ times 5 higher than the GBW of the FET controlling opamp, so I tried this approach in my simulation but again I got oscillations… (also this “rule” is not being followed in the HP 6060B at all)

So to understand this problem better it would be very helpful if someone could help me out with these question :
What is the main difference between the high speed solution of LT and my low speed one (except for the obvious difference in GBW)?
Why is my solution oscillating and the LT one not?
And why does the LT solution doesn’t look good in the AC analysis although it behaves well in the DC analysis?

Thank you very much in advance!
Kind regards

[Kleinstein]

With the 2 OP control loop it is still possible to use a rather slow OP for the DC precision and a fast OP for the AC part. In you old (V4) file just use appropriate values for R3 and C1. These two give an AC feedback path that bypasses the DC amplifier. With something like 1 K and 10 or 100 nF, I got a stable loop at my first try.

With a very fast loop you have to be careful with parasitic effects. At low impedance (e.g. the shunt) minute extra inductance can make a big difference. So one might need to use a higher value shunt for this reason.

The difference in the two shown simulations is that the first try with a lot of ringing has the phase reaching 0 degree in a range where the gain is close to 0 dB.
The circuit with faster OP is always above zero phase and has the low phase (e.g. < 3 deg) only in a range where the gain is still high. Still the response is not really good.

The transient curves are also testing the response to set point changes - no to external disturbance (e.g. jump in voltage). The first simulation is also ringing a lot only at the high current, not at the low current. The stability can depend on the DC current level.

[danadak]

In order to get precision and rejection of CM in the sense circuit consider
using an IA. They are laser trimmed and produce very high CMR, nowadays
a single G set R is used, with excellent rail preformance.

Your discrete circuit, R variation, Aol variation, can produce some real crappy
CMR performance.

Attached an analysis.


https://www.dropbox.com/s/plck7e95v7pw33c/CMR%20Analysis%20IA.pdf?dl=0


Regards, Dana.

[electricar]

With the 2 OP control loop it is still possible to use a rather slow OP for the DC precision and a fast OP for the AC part. In you old (V4) file just use appropriate values for R3 and C1. These two give an AC feedback path that bypasses the DC amplifier. With something like 1 K and 10 or 100 nF, I got a stable loop at my first try.

Is it possible that you got the stable loop with 0A of current through the FET?
With e.g. 2A mine is very unstable.
Perhaps you could attach your simulation with the stable loop?

With a very fast loop you have to be careful with parasitic effects. At low impedance (e.g. the shunt) minute extra inductance can make a big difference. So one might need to use a higher value shunt for this reason.

Ok thanks. I'll pay attention to that.

The difference in the two shown simulations is that the first try with a lot of ringing has the phase reaching 0 degree in a range where the gain is close to 0 dB.
The circuit with faster OP is always above zero phase and has the low phase (e.g. < 3 deg) only in a range where the gain is still high. Still the response is not really good.

Why is the response still not good? Do you mean the transient response? As far as I know the stabilty criteria is a PM of >45° and a GM of >10dB. Is this right?

The transient curves are also testing the response to set point changes - no to external disturbance (e.g. jump in voltage). The first simulation is also ringing a lot only at the high current, not at the low current. The stability can depend on the DC current level.

I'm simulating the changes in voltage too in another file. I noticed the instability at higher currents also, but 5A per FET is my requirement, so I have to get it stable

In order to get precision and rejection of CM in the sense circuit consider
using an IA. They are laser trimmed and produce very high CMR, nowadays
a single G set R is used, with excellent rail preformance.

Your discrete circuit, R variation, Aol variation, can produce some real crappy
CMR performance.

Attached an analysis.


https://www.dropbox.com/s/plck7e95v7pw33c/CMR%20Analysis%20IA.pdf?dl=0


Regards, Dana.

Thank you Dana for this hint and the interesting analysis

I'll make a little PCB and test some different opamps in combination with different IAs like the AD8221.

Kind regards

[cezar]

I am in a process of designing my own DC load. I came across this video . Author describes why switching MOSFETs should not be used in DC load applications.
Any thoughts on this? Is the positive temperature co-efficiency really an issue?   

[Kleinstein]

Getting the output stage stable even to higher currents turned out to be difficult. One thing needed to go to 5 A, is to give the OPs a little more voltage (that is easy). The problem I found is that the MOSFET is quite nonlinear - having a much higher forward trans-conductance at higher current. The normal way to reduce this problem is to have a resistor at the source (higher than the shunt). However this limits the minimum voltage. I tried a version with an inductor + damping instead - not sure there is a real catch with this.

Somehow LT spice had a problem with the OP-model for the AZ OP - so I set it to the universal OP. It failed to find an operation point some times - this could be due to too much DC gain in the loop. I removed the reverse polarity check too - as it slows down simulation and I had the suspicion it was the cause of finding the DC point. It should not have a negative effect on stability. The inductor L2 is included for parasitics of a shunt. Not really needed for stability.

For looking at the stability I did the simulation with variable external voltage. The current source should be stable if the phase shift is withing +-90 degree of a resistor. Plotting the current (e.g. at the resistor at the input) directly gives the conductance.   With some optimization I found a reasonable solution, still not too critical in the parameters.
The damping RC at the input could actually be chosen higher impedance  - which is usually considered good. The old RC have been a problem too with to low a resistor and thus working effective only at to high frequencies.

I have not tested much on changing the DC level - this could also change things a little, especially at very low voltage. So there might need to be a kind of under-voltage lock out.

PS: there is downside in having the inductor at the source: one can not change the current fast very good anymore. So the CV mode might not work well.

[electricar]

Hello cezar,
this is a nice video! The transfer characteristics are indeed a „problem“ when using normal switching FETs which were not designed for linear operation. That’s why the professional DC loads from Agilent and BK Precision use a higher quantity of them in parallel. They just design very conservative and add extra margin through spreading the power on more FETs.

The linear FET in the video is looking really interesting and I’m thinking about ordering one or two to test them out by myself (but the smaller one, IXTH75N10L2).

The only thing I don’t understand is that the input admittance he is talking about to be bad on the switching FETs, is similar at the linear FET (see IXTK90N25L2.png).

It also looks like a higher temperature is leading to a higher drain current when keeping the same Vgs. Why is this not an issue with this linear FET?

Also the liner FET which would suffice for my application (IXTH75N10L2) has almost the same BTZ as the IRFP250N which is not designed for linear applications (see IXTH75N10L2.png). And because the gate voltage will be normally under this point in a DC load, I expect the same behavior (a higher temperature is leading to a higher drain current when keeping the same Vgs).
So again, why is this not an issue? Does it have to do with the internal construction which is different to the switching FETs?

@Kleinstein:
Thank you very much for your great effort!
I didn’t manage to look at your simulation yet in more detail. As soon as possible I will have a deeper look

Kind regards

[Kleinstein]

With most MOSFETs the current at constant gate voltage goes up with temperature. The difference is in how fast the current goes up and how even the current is distributed to start with and how much testing is done.

The "switching" FET used in that video is an IRFP150 - this actually a type that is not that bad for linear operation. It is more or less a lower voltage grade of the IRFP250, which is considered a reasonable choice for linear operation if you don't want to pay the hight price of the linear rated FETs. That particular DS was missing the DC curve in the SOA diagram - but at least Fairchild includes the DC curve and has the extra note that the DC SOA is limited by Ptot.

A really bad choice are the modern low voltage switching MOSFETs like IRFP7430 - it has a DC SOA curve, but this shows the limitations.