Best practices: Schematic vs Footprint layout?

[onesixright]

Hey All,

I'm creating my own libraries for components.  When using standard component I see sometimes the pin layout is different then the footprint layout. In my experience, once you then move to PCB layout, this can bite you in the ass. Pin positions can then be different, which can make the routing cumbersome.

My questions (as a rule of thumb):

1. Is it better to just follow roughly the footprint layout (i understand you can have multiple packages for a single components)?

2. And more general: wouldn't it be easier to always keep  in mind the traces when starting with the schematic layout?

Curious how you guys approach this, any best practices?

Thank you all!

[sokoloff]

It's not always easier to keep the package layout on the schematic.

Take an op-amp. It's much clearer to have the schematic have the + and - inputs in a "logical" place on the schematic, regardless of how they are pinned out in the package. For me, schematic drawing is logical and doesn't need to reflect the physical.

[suicidaleggroll]

On devices that have to be hooked up a certain way it doesn't matter, that's what it has to be.  The schematic symbol should be drawn however makes the schematic easiest to follow with no regard for the physical pin layout, because the physical layout is going to be what it is going to be and nothing you do with the schematic symbol will change that.

On devices with flexible pinout (GPIOs on MCUs, FPGAs, etc), I generally leave the pins on the schematic disconnected until the layout is to the point where I'm ready to route those signals, then I use the current layout and physical component locations to decide which pins will make routing the cleanest/easiest/best, hook them up in the schematic, re-generate the netlist, and then complete the layout.

[Benta]

My way is to make the schematic logical and readable without thinking of the PCB layout. Important is, that when you want to service your design in 5 years, you'll understand the functionality at a glance.

Concerning layout, the "rat's nest" function is the best thing ever invented. Do your placement  for simplest routing, for many ICs there is only one way to connect them.
When all this is done, I look at the "multiple part" ICs, eg, dual/quad opamps, multiple gates, dual flip-flps etc., and with help from the rat's nest start looking at possibilities of better routing if you swap gates, for instance. I've usually done some routing at this point already to get "no-brainer" traces out of the way, reducing clutter.
When this is done I continue routing and layout, perhaps having to do a couple of more gate swaps along the way.
When finished, it's "back annotation time", meaning bringing the changes done while routing back into the schematic (this is mainly updating the pin numbering on the swapped gates).
If you have an integrated schematic/layout package, this can normally be done automatically. Otherwise it's just boring work :-)

[dmills]

Schematics are made for humans to read, make them logical and don't worry about the physical pinning.

Signals flow from left to right, use a sane grid, bus related things, use line thickness to make it clear what is real power trace and what is small signal, if your tools support it then colour can be helpful to group particularly interesting nets.
If you have hierarchical design in your tools, use it with the top level being essentially a block diagram and a whole mess of individual sheets each containing one functional block.

Do not be afraid to put notes on the schematic, in particular notes about how values were calculated and what voltage ranges should be found on test points and the like are helpful when fault finding. A note on a power rail for example saying something like (11.8V - 12.3V) tells someone fault finding what the expected range is, without having to dig out the calculator.

I am a big fan of actually using the pin type stuff so that ERC will give me useful output, you generally do not get a totally clean report (Most ERC does not handle mixed signal well), but knowing you should have X errors and seeing that after some change you have X +3 errors on the ERC report is useful.... To make this work you generally have to create a local library copy of the more complex sort of chip so you can set the pin types as they will be programmed, but it is worth it.

When it comes to layout time, placement is **EVERYTHING**, get it right and the board will almost route itself, and I concur that rat lines are an excellent thing.

Back annotate can be very much your friend especially when you have a package with multiple gates, and for more complex things I am not above going back and editing the pin names and designators in the local library schematic part to make both the schematic and the board look right.

Regards, Dan.

[basinstreetdesign]

One thing I simply detest is fractionated schematics.    You know the ones.  We've seen them here.  The schematic consists of many, many small schematic pieces each with several signals ending in schematic signal names.  The same-named signals are not connected with lines as they should be.  The worst ones are several pages of this.  This results in spending an inordinate amount of time hunting for, and trying to memorize the other places where those signals are used.  The schematic is practically unreadable.  They should be re-drawn and properly organized with everything connected with lines (except perhaps grounds and some power rails), with signal flow from left to right and top to bottom.

But as others have said before, the schematic symbols need have no correlation to their physical embodiment.  So please do NOT use a little physical picture of an IC as a schematic symbol.  Especially those that have no pin function labeling as they are completely useless to anyone trying to divine what the circuit is supposed to do. 

[H.O]

It's pretty clear that the sole purpose of SOME schematics is to go from design to layout and finished board as quickly as possible but I suppose it depends on what you're doing.

I've just spent a couple weeks doing the exact opposite of what you suggest. Redrawing a schematic of an electrical control system (relays, switches, contactors, temperature controllers, motors, valves etc) from an almost unreadable 2x1.5m single sheet schematic to a ~20 page function based schematic....much better when you're trying to understand how the system works in order to troubleshoot and modify it IMHO.

As the complexity of the circuit goes up, trying to fit everything that's electrically connected onto a single sheet with actual lines for each and every connection sooner or later becomes a mess.

[AndyC_772]

I tend to apply different "rules" to different kinds of device.

For example, an op-amp is a well known device with a universally recognised symbol, so that's what I use, regardless of the physical pin-out of the chip. I'll split the symbol into parts, so a dual op-amp will have three parts to the symbol - two individual amplifiers, and a third symbol which has the power and ground pins.

Power supply components (eg. SMPS controllers) are drawn with whatever pin arrangement makes the schematic clear and easy to read. Usually this means drawing them something like the example schematics in the data sheet.

Microcontrollers, on the other hand, I'll draw with the pins in their physical order, again with power pins separated out to another symbol.

FPGAs are split up into a number of symbols, each of which corresponds to one I/O bank. Since each bank can be powered from a different I/O voltage, splitting up the symbol this way makes it easier to avoid mistakes in designs using multiple I/O voltage levels.

Complex microprocessors are split into multiple symbols, where each symbol corresponds to a different function. So, for example, the DRAM interface will be on one symbol, external Flash interface on another, GPIOs on another, and so on. Chances are the device is a BGA anyway, so placing pins per their physical position would be nonsense.

As an aside: I once found myself working for a company which had a policy on schematics: inputs on the left, outputs on the right, always. So, if a processor had pins for a crystal oscillator, XIN would go on the left, XOUT on the right, and the resulting ugly circuit was unavoidable because symbols would be drawn by 'trusted' component librarians rather than the engineers themselves. I protested, and won a small bonus for my efforts to improve company procedure - but no actual change. To my knowledge, a well-known network equipment manufacturer's Pierce oscillators still look like crap on their schematics to this day.

[james_s]

As an aside: I once found myself working for a company which had a policy on schematics: inputs on the left, outputs on the right, always. So, if a processor had pins for a crystal oscillator, XIN would go on the left, XOUT on the right, and the resulting ugly circuit was unavoidable because symbols would be drawn by 'trusted' component librarians rather than the engineers themselves. I protested, and won a small bonus for my efforts to improve company procedure - but no actual change. To my knowledge, a well-known network equipment manufacturer's Pierce oscillators still look like crap on their schematics to this day.

That sounds like something a government entity would do.

How did they handle bidirectional pins? Draw them in the middle sticking up into the Z axis?

[dmills]

One thing I simply detest is fractionated schematics.    You know the ones.  We've seen them here.  The schematic consists of many, many small schematic pieces each with several signals ending in schematic signal names.  The same-named signals are not connected with lines as they should be.  The worst ones are several pages of this. 

Oh god yes, had one of those stupid things delivered recently by a conslutant at work, it was completely unreadable, tiny little stubs with net names (Including stubs on no connects, just to make it even harder to see what mattered, named things like NC156), and not helped by not using power or ground symbols, just a net stub labelled gnd, took two engineers a week trying to review the stupid thing and we still missed stuff that mattered.

Net labels on stubs have their place, but it is mostly global things like clocks (And even then a hierarchical sheet entry should probably be considered), not every net on the damn board.

In much the same way as one writes source code primarily to be human readable, one should attempt to draw schematics to be human readable.

I really, really wish the schools would start spending just 1 module on how to communicate technical information, it is an utterly vital skill.

[james_s]

Uhg, I hate those too. It's not something I encounter often but I've been troubleshooting the power supply for a TDS420 scope using the service manual for a LeCroy with a very similar PSU and the regulator is broken up like that in the schematic. Why, I have no idea, they could have easily just drawn a dotted line around the portion located on the vertical daughterboard.

[KL27x]

Unless the circuit is very simple and/or your brain works differently from most of us, it really doesn't help to work with a symbol that matches the footprint. You can swap connections in the schematic, later, once you're partway done with the routing and actually identify an improvement. (And you can change it back and forth 10 more times while trying to route the last signal.)

[AndyC_772]

How did they handle bidirectional pins? Draw them in the middle sticking up into the Z axis?

If I recall correctly, yes, that's exactly what they did.

I'm not sure whether to laugh or cry, so instead I'll just leave these here.

        

[onesixright]

Hi All.

Just a thank you note for all the feedback, awesome! I'll take the advise to heart! Till now I often was thinking about routing issues, in the schematic phase. But after-all, your right, once the components are set, they need to be routed. The schematic will simply not change that 

[james_s]

How did they handle bidirectional pins? Draw them in the middle sticking up into the Z axis?

If I recall correctly, yes, that's exactly what they did.

I'm not sure whether to laugh or cry, so instead I'll just leave these here.

        

Wait, what? I make up the most absurd way of doing it that I can think of, and you're telling me that's what they actually did?!

[AndyC_772]

Hi All.

Just a thank you note for all the feedback, awesome! I'll take the advise to heart! Till now I often was thinking about routing issues, in the schematic phase. But after-all, your right, once the components are set, they need to be routed. The schematic will simply not change that 

It's common to make schematic changes during the layout phase. It may, for example, not matter which GPIO pin is used on a microcontroller to drive some external device, but a smart choice of pin-out may save headaches in the PCB layout phase.

I design a lot of boards these days which are little bigger than a postage stamp, and which are packed with components on both sides. There's no room for superfluous vias, and I have to consider pin allocation very carefully (and be ready to change it during routing).

Wait, what? I make up the most absurd way of doing it that I can think of, and you're telling me that's what they actually did?!

Feel free to bang your head repeatedly against the nearest solid object. I did.

[BrianHG]

For my largest FPGA board, using an Altera 780pin bga, I had my fpga in the schematic layout as a grid, with color coding for the IO bank separation, features, power pins & special purpose pins.  My simm ram modules also were in their shape dual inline shape, color coding the GND/VCCint/VCCio&pll, 128 bits worth + 36x4 data buss x4 IO on the left and right side of the chip.  I use 98% of the IOs on the FPGA and did it on a 6 layer board.  I don't recommend adopting this practice, but it did make what should have at least been a 12 layer board only 6 with minimal vias.

The PCB looked great, but, verifying the schematic was a little difficult.  The only thing saving me here is that I use 'proper intelligent net names' on all the IO signals & used the netlist generated in my Protel PCB cad to set the net names in Quartus eliminating mistakes for the over 350 IOs in use.  (I made a little BASIC script software to isolate the FPGA pin#s and NET names to generate a Quartus compatible Verilog and pin assignment editor .cfg file declaration eliminating all errors except for the reserved JTAG pins names.)

[KL27x]

It may, for example, not matter which GPIO pin is used on a microcontroller to drive some external device, but a smart choice of pin-out may save headaches in the PCB layout phase.

+1. Also, you have your IC arrays (e.g. quad comparator) and the pin layout can be pretty much anything.