BLDC Motor Controller, Design, Waveforms, Thermal Tests

[Glenn0010]

Hi all this is my first post here,

I am doing my final year thesis in electronics and control. I have built a prototype board for my BLDC motor controller. The board has a lot of test points and jumpers so I can manipulate components in and out of circuit to see what effect they have on the wave forms.

What I want to test for now is:

1. The effect of the electrolytic capacitor in parallel with the ceramic bootstrap capacitor.
2. The effect of the diode in parallel with the gate resistor
3. Effective Snubbing to have clean 'power' wave froms

Below are the schematics:





And here is my soldered board:



I tested the functionality of all the FETs using a 10 Ohm load resistor. I put the probes across the load resistor and here are the waveforms I got:




I measured the ringing frequency at around 13.2 MHz. I obviously want to eliminate this ringing and that nasty voltage spike. My FETs V_DS is rated at 100V however I want to eliminate this.

I have read several papers and application notes on Snubbing and from what I understood and from the equations it seems that the voltage spike and ringing is to do with the stray inductances of the components traces etc (L_LK).


I have used this AN from NXP as my main guide. https://assets.nexperia.com/documents/application-note/AN11160.pdf


I do have some questions though:

1.Do I just need an RC snubber circuit across the high side FETS as the NXP AN seems to State?
As this document from TI seems to inidcate that the RC snubber should be placed across the low side FETs : http://www.ti.com/product/CSD88599Q5DC/datasheet/layout?

An I have found this source that indicates snubbers across both sides


2.Could I get away with placing just 3 ceramic caps across each half bridge as I just have big fat electrolytics across the POWER rail which are useless for this kind of thing.?

Sorry for the questions but I am a bit confused.







+ Attachments and other options

[Floyo]

It looks like the layout might well be the cause of your issues, it is rather "loose" and spread out. The trace inductance between the gate driver and the fet will form a resonant network, which is one of the potential sources of your issues. The other is the stray inductance in the power section. As I can see straight through your board, I assume there is no ground plane, and your power traces meander about quite a bit too.

I suggest you read up a bit on power pcb design. The idea is to minimise trace inductance by keeping the "loops" short. Every current that flows in a conductor has to return to its source.
Inductance is influenced by a few major factors, length and area being the main ones. So to get low inductance we want to have a return path right next to, or underneath its source.
Since the return path is often ground a groundplane on the bottom or inner layers will provide a good path for most signals (provided it is not broken into many pieces by traces).
For other return paths, such as your high side drivers the same still applies, but your return path is now the bridge mid point.

Your schematic looks quite decent otherwise, though I would remove the jumpers for components you can just solder in as needed, such as the caps and diodes. This so you can squish stuff together tighter.
I would also add some MLCC caps to your bridge decoupling strategy, the electrolitics alone might not be good enough with regards to ESR and inductance.

Once you get all of this under control you can start to think about snubbing what is left of your resonance, but right now its a bit of a patch for a poor layout.

Oh, and a final note. Maybe test stuff with a current limited bench supply, not with what I assume is a RC lipo battery going by the vaporised trace . This saves on fireworks, better yet would be some current protection built in to the design, so faults in the load are covered too.

Edit:
As quick run through the numbers shows the 13ish Mhz is correct for the trace inductance you have in the power section. plugging some guesses for your board into there (3mm width, 9mm separation and 4cm length) gives 151nH your bridge output capacitance is 880pf (two fets), so that gives 13.8Mhz.

[Glenn0010]

It looks like the layout might well be the cause of your issues, it is rather "loose" and spread out. The trace inductance between the gate driver and the fet will form a resonant network, which is one of the potential sources of your issues. The other is the stray inductance in the power section. As I can see straight through your board, I assume there is no ground plane, and your power traces meander about quite a bit too.

I suggest you read up a bit on power pcb design. The idea is to minimise trace inductance by keeping the "loops" short. Every current that flows in a conductor has to return to its source.
Inductance is influenced by a few major factors, length and area being the main ones. So to get low inductance we want to have a return path right next to, or underneath its source.
Since the return path is often ground a groundplane on the bottom or inner layers will provide a good path for most signals (provided it is not broken into many pieces by traces).
For other return paths, such as your high side drivers the same still applies, but your return path is now the bridge mid point.

Your schematic looks quite decent otherwise, though I would remove the jumpers for components you can just solder in as needed, such as the caps and diodes. This so you can squish stuff together tighter.
I would also add some MLCC caps to your bridge decoupling strategy, the electrolitics alone might not be good enough with regards to ESR and inductance.

Once you get all of this under control you can start to think about snubbing what is left of your resonance, but right now its a bit of a patch for a poor layout.

Oh, and a final note. Maybe test stuff with a current limited bench supply, not with what I assume is a RC lipo battery going by the vaporised trace . This saves on fireworks, better yet would be some current protection built in to the design, so faults in the load are covered too.

Hey thanks so much for your reply.

I know my PCB design wasn't ideal. I needed those jumpers, so I can test the electrolytic bootstrap cap and the diode to see what difference they make.

Also I didn't include any power planes since I never worked with the UCC20520 before and wanted to make sure I got it functioning and I thought having no power planes would make it easier to troubleshoot had any faults occurred.

Is the magnitude of the ringing solely determined on the trace/package inductance? Or will the magnitude of the voltage spike be increased if I used a BLDC motor as a load?

My plan was to test these components and apply a snubber circuit.  Then test again my old BLDC motor code for sanity and redisgn a proper, small low inductance PCB. However it seems that you think that I should start with that. Obviously I want to design as few PCBs as possible for costs etc.

I think a good compromise wold be to test the diode and electrolytic cap, test the code and make a proper pcb which will include the Uc as well. Then leave some pads on the PCB to calculate the scrubber?

Oh yeah I'm using an ebike 18650 pack as my supply as I don't have a proper supply at home. The idiot that I am I tried to measure the deadtime on the outputs and shorted the supply through the scope.

Thanks again!

[Siwastaja]

You need to realize that the need for RC snubbers in a hard-switching bridge circuit like that is often mainly to compensate for layout problems. Thus, the style of snubber used, and the value of components needed, are highly dependent on the layout. (Snubbers may also be needed to compensate for the nonidealities of the semiconductors, but because the layout probably dominates, you can't test that!)

So, normally you'd start by designing a proper layout - then adding snubbers as needed.

Your layout looks like a total catastrophe, sorry. On the other hand, this helps produce clear results on what kind of snubbing helps in this kind of "extreme", totally failed (sorry!) circuit design; but on the other hand, the implications cannot be directly used, since the style and magnitude of issues will be different.

Snubber components themselves need to be as low inductance as possible, making "socketing" or switching between them useless, because the extra inductance invalidates the practicality of the results. Thus, the only way is to lay the snubber components out properly - you'll need to desolder/solder them as you go, but that's not a big deal since you are probably not going to go through tens of different snubbers.

So, in my opinion, you are approaching this in the completely wrong way, exact opposite to what actually makes sense (and how it's normally done, too). While you may think that the layout is only "kind of" important, it's not; it's actually the meat here; all you are trying to measure and study is completely based on your layout!

Even if you accepted the poor power layout (which could make some sense, since you are trying to fix issue caused by it by using the snubbers, after all!), you'd need to do the snubber layouts as well as possible.

I know that learning about a good power layout may look like an overwhelming task, so let me give you a single tip which will lead you in the right direction: DC bus (your battery voltage) - think about it as two parallel plates, like a capacitor. If you insist on 2-layer design, then it'll be two wide (several inches, if you wish!) fills, one on the bottom layer, one on the top, with only the thickness of the board between them. Fill it with DC bus capacitors (using vias to connect to the "other side", there will be small cutouts then), going directly between the two "plates". This might not be the final or optimal design, but draw it, and your mindset will be in the right place, when you force yourself to add the semiconductors between these plates with almost negligible distance and hence, stray inductance.

[Glenn0010]

You need to realize that the need for RC snubbers in a hard-switching bridge circuit like that is often mainly to compensate for layout problems. Thus, the style of snubber used, and the value of components needed, are highly dependent on the layout. (Snubbers may also be needed to compensate for the nonidealities of the semiconductors, but because the layout probably dominates, you can't test that!)

So, normally you'd start by designing a proper layout - then adding snubbers as needed.

Your layout looks like a total catastrophe, sorry. On the other hand, this helps produce clear results on what kind of snubbing helps in this kind of "extreme", totally failed (sorry!) circuit design; but on the other hand, the implications cannot be directly used, since the style and magnitude of issues will be different.

Snubber components themselves need to be as low inductance as possible, making "socketing" or switching between them useless, because the extra inductance invalidates the practicality of the results. Thus, the only way is to lay the snubber components out properly - you'll need to desolder/solder them as you go, but that's not a big deal since you are probably not going to go through tens of different snubbers.

So, in my opinion, you are approaching this in the completely wrong way, exact opposite to what actually makes sense (and how it's normally done, too). While you may think that the layout is only "kind of" important, it's not; it's actually the meat here; all you are trying to measure and study is completely based on your layout!

Even if you accepted the poor power layout (which could make some sense, since you are trying to fix issue caused by it by using the snubbers, after all!), you'd need to do the snubber layouts as well as possible.

I know that learning about a good power layout may look like an overwhelming task, so let me give you a single tip which will lead you in the right direction: DC bus (your battery voltage) - think about it as two parallel plates, like a capacitor. If you insist on 2-layer design, then it'll be two wide (several inches, if you wish!) fills, one on the bottom layer, one on the top, with only the thickness of the board between them. Fill it with and DC bus capacitors (using vias to connect to the "other side", there will be small cutouts then), going directly between the two "plates". This might not be the final or optimal design, but draw it, and your mindset will be in the right place, when you force yourself to add the semiconductors between these plates with almost negligible distance and hence, stray inductance.

Thanks so much for the feedback! I knew my layout was a mess, ut I guess I did not realize how much of a difference it would make. So I shall abandon the scrubber design until I run the other tests, test my 6 step commutation code again and implement the SPWM in code. Then I shall design a proper board with the Uc included and proper layout.

1 Can I test the BLDC motor at 48V or will the added inductance of the motor produce even bigger voltage spikes and exceed the VDS of my FETS? or is it solely reliant on the stray inductance.
 
2 Do you have a recommendation on how to include the snubbers on the final board version. Snubber caps and resistors are fairly low in values typically so I can use the 1206 package. Shall I just place the footprints on the board for the final layout and the solder and desolder as needed?

PS do you think this is a good procedure ot go about things?

Thanks so much for the feedback! looking forward to improve this mess

[Siwastaja]

Add the motor but run at much lower voltage first to measure the spikes without blowing up the devices. Note that the actual spike can be higher than your scope shows.

Nothing prevents you from running at, for example, just 4-5 volts first. This also limits current by the winding resistance so that you can test if your active current limiting works before actually blowing anything up. At full voltage, the current through the winding resistance is so high that the fets will blow up instantly if your current sense doesn't react in a few hundreds of microseconds, and the motor inductance saturates. Ramp up the voltage, see how the spikes are at 10V. If they are at 20V, you can expect they'll be at least at 96V when 48V is applied. As a first-order simple guesstimate, at least .

Really work on the layout. I have never used any RC snubbers in a motor control bridge, never found any need to use one. You can add some 1206 or even just 0805 package RC snubber over the FETs, as close as possible - but never compromise the layout by adding the snubbers.

As you are not manufacturing the PCB by yourself, there is no reason not to use 4-layer board. Once your layout is properly done, your board will be so much smaller that the 4-layer manufacturing isn't probably any more expensive than the 2-layer manufacturing currently is for you.

4 layers will give you a nice low-inductance top layer + mid1 (or bottom + mid2) pair to form the DC bus I wrote about earlier, the gap between the layers will be very small; and you'll still have two layers left so you can easily route short gate drive connections! Use a lot of vias when you need to jump between layers, both from the inductance & resistance viewpoint. Basically, I try to dedicate both mid layers as ground planes, only doing short traces in only one of them, since a motor driver won't have too many things to route.

[max_torque]

 I guess I did not realize how much of a difference it would make.

The thing is to understand is that the faster you want to change the current that is flowing through any objected, the more that objects inductance matters!  (for an inductor V = L di/dt,  ie the voltage generated across that inductor (V) is proportional to the objects inductance (L) multiplied by the rate of change of current (di/dt))

The reason this REALLY matters for any switching circuit is that semiconductors would rather be fully OFF or fully ON, the bit in the middle where they effectively have some resistance is a bad area to operate in, because the loss across that semiconductor is massive.  (when it's OFF, and no current flows, there is no loss.  When it is ON, current flows, but it's resistance is tiny, so the losses are manageable, but when it is conducting current but with high resistance, it has a high voltage drop and so a massive power loss).  Hence, all switching circuit designers have to make a trade off between fast switching as fast as possible to minimise losses  (the fundamental frequency itself is not that important but what is important is the time it takes to switch from conducting to non conducting) and switching slower to avoid voltage spikes and EMC/EMI issues.

Consider a Switch with 10 amps flowing through it, when we turn it off, in say 1 microsecond.  The rate of change of current, di/dt, is 10 amps / 0.000001 seconds, which is 10 MILLION amps per second!  So even a tiny amount of stay or parasitic inductance, even in the nanohenries, will generate a significant voltage across it.

Your job as a circuit designer is to make the necessary design trade offs and find a suitable layout where you can switch your semiconductors at the rate you need to get to your efficiency or thermal performance targets.  Poor layout with intrinisic inductance that cannot be designed out is often compensated for by slowing down the switching time of the switches (using larger gate resistors) but this increases the thermal loading, and reduces efficiency.  In the worst case, you may have to de-rate your device to a lower current capability in order to prevent voltage overshoots and over heating.

[Floyo]

I don't have much to add to the above, sound advice.

As for your wanting to test the influence of certain parts, ask yourself why you would need them. Does the datasheet suggest them, or does the math say you need them? etc.
In prototyping its a good idea to leave some flexibility in the design, and gate drivers especially benefit from some extra footprints between them and the gate. But always keep in mind why you are doing what
you are doing, don't just try it. Do some back of the envelope math with rough guesses, or even a quick simulation to figure out what something should do . You might do the right thing for the wrong reasons otherwise, or get led down the garden path by a misunderstanding.

If you want some inspiration, have a look at the Vedder ESC, the design files are available as is the code as I recall. Notice how that design has current limiting for example that will save your fets/pcb from exploding, also the layout is compact. I'm not saying its the best possible BLDC solution, but it might be a good place to start taking inspiration from. Also have a look at app notes from the semiconductor manufacturers, they often have suggested layouts and schematics for their development boards.

[Siwastaja]

Yeah, having looked at your schematic again, it seems to lack current limiting. I was assuming it has it, without looking, since it's basically 100% mandatory.

Using a mosfet driver with a so-called "desaturation detection" will do well enough, or you can add separate low-side shunts and amplifiers.

But you need to measure current at some usable accuracy (such as +/- 50%) and be able to react to it in maybe about 50-100 µs. Otherwise a few wrongly calculated PWM cycles, and all your MOSFETs are dead -- and even good, tested algorithms cannot guarantee they can work out correct PWM cycle calculations without relying on current limiting, let alone development work!

[Glenn0010]

Thanks all for the great advice!!

I had planned the current limiting but have not got round to using it yet. I was planling to use the ACS hall effect ICs however in a compact board I'm thinking that the magnetic fields through the traces might lower the accuracy. I was planning to use just 1 sensor on the negative wire leading to the battery just for current limiting purposes.

I have seen the Vedder Board and that thing is a work of art and is something I am aiming towards.

Do I add snubber footprints for both the low and high side mosfets just in case?

So here is how I will proceed.

1. I will add 100nf MLCC acros + and - of each half bridge, maybe that will help a bit just to make things safer for when I am running the motor.
2. I will run the motor at low voltage to begin with (say 12V) and monitor the voltages. (Do I need to monitor for example across one high side mosfet Vds or do I monitor between mosfet pahses?)
3. I will add current sensing and limitng.
4. Implement SPWM using hall sensors only using angle estimation (should be fun).
5. Conslidate the PCB design with a proper layout!

I guess I can compare the voltages of the two layouts and it should give me a good comparison.

I will keep you posted.

First order of businesses Implementing the BLDC code again and re testing it

[Benta]

Just for my understanding:
I see no commutation circuitry, neither Hall-sensor nor back-EMF sense. Perhaps it's on a different part of the schematic.
Or is this in reality a PMSM design?
This question does have consequences for the driver stage.

[Glenn0010]

Just for my understanding:
I see no commutation circuitry, neither Hall-sensor nor back-EMF sense. Perhaps it's on a different part of the schematic.
Or is this in reality a PMSM design?
This question does have consequences for the driver stage.

The hall sensor circuitry is relatively simple, the hall sensors are connected to interrupt pins of the micro controller using internal pull-up resistors

[Siwastaja]

DC link input current measurement might not be quick enough, depending on the amount of capacitance directly on the bus. Of course you can place the shunt so that most of the bulk capacitance is before it.

Integrated desat is preferred since it comes automatically in many gate driver ICs and while not good enough for precise torque control, it's ok for crude current limit for protection.

I had good results using DRV8302 in my first ever BLDC motor design.

If you think about your bridge and how the motor is connected, having current sense in two of the phases, on bottom legs only (below the FET) is enough and will protect you from any faulty PWM state - of course as long as you move to a safe state when you detect the overcurrent (000, 111, ZZZ, etc.).

You get a quick start once you understand that when you map the 3 hall sensor wires (3-bit value) as an index to table[8], which gives you the rotor magnetic position directly (6 steps, 0 to 5) and use that position to index sine table at three different offsets (base, +120 and +240 degrees), and use these values as the PWM values - 50% duty is the zero point. And you have a simple and completely usable BLDC speed controller. Add a multiplier to tune the torque, and some current limit code to quickly turn down that multiplier - or, if severe overcurrent, just turn it off.

For the open collector hall sensors, that's a noisy environment, especially with a bad layout. MCU internal pullups are almost always too high in value (20-50k?). I used external 4.7k + 220R series + 1500pF ceramic cap for filtering in my first design.

[jmelson]

Yes, you want to minimize loop area to cut inductance.  I have built some similar servo drives.  I use the IR2113 half-bridge driver in some of them.  Across the low side transistor, I have an ultra-fast diode to prevent the junction of the two transistors from going below ground when the top transistor shuts off, and the load inductance wants current to keep flowing out of the half bridge.  Also, I use a 10 Ohm resistor and 10 nF cap in series as a snubber.  Note that the resistor will run hot, so I use a several Watt non-inductive part.

The inductance causing the common point between the two transistors falling below ground will burn out my IR gate driver.  Not sure that your part can handle that condition.  Do NOT trust the "body diode" in the FET, they are completely awful.  I measured forward turn-on taking several microseconds at up to 12 V!  Certainly the slowest diode turn-on I've ever seen.

Jon

[zombiess]

Eliminate all the jumpers, they add inductance.
Layout is everything in power electronics.  Gate driver design is deceivingly tricky so don't get too discouraged with your first design not behaving as you would expect.

Your layout needs to control the loop areas for gate drive signal and DC bus.  Your DC bus should overlap to minimize loop area.  High DC bus inductance will rear it's head as turn off overshoot on your drain to source pins.  While your layout needs serious work, you should try slowing down your gate-source switch time by increasing your gate resistor.  I typically target 800ns to start and work from there.  Controllers under 1kW tend to be pretty forgiving of poor layout.

Be very careful where you ground your scope since you are not using differential probes as you can damage your scope and board.  With normal probes the best way I've found to do power electronics work is to put the ground on the phase out and then invert the signal trace when making measurements on the low side.  When making measurements you don't want to use the jumper lead as it adds inductance which can show up as ringing that really isn't there.

I've designed a 7.5kW (20kW peaks) 120V DC bus controller I've been playing with for some time on an ebike and various other projects.  I've posted the schematic and Kicad layout files if you want to take a look.  I used the TD350E gate drive and ran fully isolated power supplies to all the gate drives.

There is some good discussion in this thread.  The one poster, Highhopes has done power electronics in the Aerospace world so pay attention to what he says.  He's the guy that taught me.
https://endless-sphere.com/forums/viewtopic.php?f=30&t=58341&hilit=controller

Have fun, try not to make too many plasma balls!

[Glenn0010]

DC link input current measurement might not be quick enough, depending on the amount of capacitance directly on the bus. Of course you can place the shunt so that most of the bulk capacitance is before it.

Integrated desat is preferred since it comes automatically in many gate driver ICs and while not good enough for precise torque control, it's ok for crude current limit for protection.

I had good results using DRV8302 in my first ever BLDC motor design.

If you think about your bridge and how the motor is connected, having current sense in two of the phases, on bottom legs only (below the FET) is enough and will protect you from any faulty PWM state - of course as long as you move to a safe state when you detect the overcurrent (000, 111, ZZZ, etc.).

You get a quick start once you understand that when you map the 3 hall sensor wires (3-bit value) as an index to table[8], which gives you the rotor magnetic position directly (6 steps, 0 to 5) and use that position to index sine table at three different offsets (base, +120 and +240 degrees), and use these values as the PWM values - 50% duty is the zero point. And you have a simple and completely usable BLDC speed controller. Add a multiplier to tune the torque, and some current limit code to quickly turn down that multiplier - or, if severe overcurrent, just turn it off.

For the open collector hall sensors, that's a noisy environment, especially with a bad layout. MCU internal pullups are almost always too high in value (20-50k?). I used external 4.7k + 220R series + 1500pF ceramic cap for filtering in my first design.

I am using isolated discrete gate drivers (half bridge UC20520). I get what you are saying about the capacitance. Do you think instead of shunts that the ACS hall effect current sensors would work on a small layout board because of all the magnetic fields everywhere?

I have already implemented a 6 step commutation system with hall sensors in the past. For SPWM with hall sensors I found an Application note that states you need to measure the speed of the motor and angle so you can set the 'cycle ' (frequency) of the sine wave correct?

So you put a 4.7k pull up resistor and and Rc filter on the signal wire correct? I am assuming that this was put on the PCB of the controller and not on the PCB inside the motor because of the long wire leads.

[Glenn0010]

Yes, you want to minimize loop area to cut inductance.  I have built some similar servo drives.  I use the IR2113 half-bridge driver in some of them.  Across the low side transistor, I have an ultra-fast diode to prevent the junction of the two transistors from going below ground when the top transistor shuts off, and the load inductance wants current to keep flowing out of the half bridge.  Also, I use a 10 Ohm resistor and 10 nF cap in series as a snubber.  Note that the resistor will run hot, so I use a several Watt non-inductive part.

The inductance causing the common point between the two transistors falling below ground will burn out my IR gate driver.  Not sure that your part can handle that condition.  Do NOT trust the "body diode" in the FET, they are completely awful.  I measured forward turn-on taking several microseconds at up to 12 V!  Certainly the slowest diode turn-on I've ever seen.

Jon

That is good to keep in mind. I have used the IR2184 in th epast which is similar to the 2113. For this I am using the UCC20520 by TI as it has isolation on board.

I keep the body diode in mind I'll run minimal tests on this and I'll completely redesign it. have a bit of information overload with all the good tips on this thread so I have plenty of work to do!

Thanks so much, gotta learn quick

[Glenn0010]

Eliminate all the jumpers, they add inductance.
Layout is everything in power electronics.  Gate driver design is deceivingly tricky so don't get too discouraged with your first design not behaving as you would expect.

Your layout needs to control the loop areas for gate drive signal and DC bus.  Your DC bus should overlap to minimize loop area.  High DC bus inductance will rear it's head as turn off overshoot on your drain to source pins.  While your layout needs serious work, you should try slowing down your gate-source switch time by increasing your gate resistor.  I typically target 800ns to start and work from there.  Controllers under 1kW tend to be pretty forgiving of poor layout.

Be very careful where you ground your scope since you are not using differential probes as you can damage your scope and board.  With normal probes the best way I've found to do power electronics work is to put the ground on the phase out and then invert the signal trace when making measurements on the low side.  When making measurements you don't want to use the jumper lead as it adds inductance which can show up as ringing that really isn't there.

I've designed a 7.5kW (20kW peaks) 120V DC bus controller I've been playing with for some time on an ebike and various other projects.  I've posted the schematic and Kicad layout files if you want to take a look.  I used the TD350E gate drive and ran fully isolated power supplies to all the gate drives.

There is some good discussion in this thread.  The one poster, Highhopes has done power electronics in the Aerospace world so pay attention to what he says.  He's the guy that taught me.
https://endless-sphere.com/forums/viewtopic.php?f=30&t=58341&hilit=controller

Have fun, try not to make too many plasma balls!

Thanks!

I have a 10ohm gate resistor and measured a rise time of around 200ns. Wouldn't increasing the gate resistor increase the rise time and drastically increase the switching losses. I am running a switching freq of 32 khz but am thinking of winding it down to 25kHz (I just hate the switching sound at low freqs)

 Thanks for the info about the jumpers, how do you recommend I take measurements on parts without these jumpers to avoid this problem?

I am also using full isolation. I am running the UCC20520 it is fully isolated. U sing a 15V to 5V isolated DC to DC for my isolation.

I'll take a look at your thread in detail and use it for inspiration.

[zombiess]

I also suggest reading through this PDF as it covers some really good info on designing a gate drives, but unfortunately does not cover component layout. 
http://www.ti.com/lit/ml/slua618/slua618.pdf
Layout is absolutely critical on a gate drive.  Even something as minute as orienting capacitors in one direction vs another can matter due to inductance.
I don't see any ground planes on your board beneath the gate drive traces, this is pretty much mandatory, but must be done correctly.  The way you attach ground planes to the power devices can matter as well depending on power level.  The gate/source connections (drain too if using a drive with a desaturation feature) are typically made similar to a kelvin type connection used to measure resistance to help minimize noise intrusion onto the ground plane.

I want to point out a safety issue (not much of an issue on your low power design) that you'll hopefully read up on more.    You are running traces underneath the gate drivers which reduces the isolation on your devices.  You NEVER run anything under a device which provides electrical isolation.  Often times you'll see slots cut in the PCB to aid in isolation. What you should see on your board if you hold it up to the light is opaque spots where your power pass section, translucent spots where your isolation barrier is.

To answer your questions:
A higher value gate resistor will increase the rise/fall time.  Your ringing is really bad.  Slow your switching time down to 800ns and see how that changes the ringing and overshoot. General rule of thums is you only switch as fast as you need to.  If I'm reading it correctly your +20V overshooting after turn off on a 48V DC bus.  No good.  Ringing = making noise= the enemy.  You should not need any snubbers for this project other than something like a 1-5uF polypropylene cap on your bus as close to the switching devices as possible.  Your DC link caps should not have any leads showing due to inductance.  Best type of cap for DC link is polypropylene, but enough electrolytics will get the job done if you don't care about cap life or have low ripple current.

To make measurements, use a probe holder of some sort and this type of lead if possible

  Make your own ground leads like this out of solid copper wire and solder them in the place you want to measure.  Short leads is the key.  If you have access to differential probes, use those, they make life so much easier.

You should consider also use 2 different bypass capacitor values 10/100nF on the gate drive power pins as close as possible to the driver chip.  A larger 10uF ceramic cap would also help with instantaneous current demand.

If you want to really learn this stuff, study Maxwell's equations and think about the physics at play.
This video does a good job illustrating the physics.

[Glenn0010]

Hi all

First of I'd like to say a big thanks to all of you that replied I learned a lot from this tiny thread and will be looking to make these improvements.

Firstly however I am testing the effect of the electrolytic bootstrap capacitor in parallel with the ceramic bootstrap capacitor and tomorrow the 'turn of gate resistor diode'

I have taken measurements using the scope my RIGOL DS1054z and the results are pretty evident as seen below. (I took the measurements with the regular probes and I know these may not be ideal but they will do for this testing phase)

The only problem seems to be that the sampling rate on my scope is too low. I tried increasing the memory depth but all it does is add more cycles. Is there anyway to fix it? If I use the averaging sampling technique I think that might ruin my render measurements null? 



Like this maybe it doesn't look so bad!



Do you think this is good enough to presnet in a thesis if I add the average sampling function to counter act that I am probing from the headers which add inductance?
Thanks!

[max_torque]

You may be aware of it already, but this blog:


http://scolton.blogspot.co.uk/p/motor-controllers.html

by Shane Colton covers a wealth of "DIY" motor controller design and experimentation!

[Glenn0010]

I also suggest reading through this PDF as it covers some really good info on designing a gate drives, but unfortunately does not cover component layout. 
http://www.ti.com/lit/ml/slua618/slua618.pdf
Layout is absolutely critical on a gate drive.  Even something as minute as orienting capacitors in one direction vs another can matter due to inductance.
I don't see any ground planes on your board beneath the gate drive traces, this is pretty much mandatory, but must be done correctly.  The way you attach ground planes to the power devices can matter as well depending on power level.  The gate/source connections (drain too if using a drive with a desaturation feature) are typically made similar to a kelvin type connection used to measure resistance to help minimize noise intrusion onto the ground plane.

I want to point out a safety issue (not much of an issue on your low power design) that you'll hopefully read up on more.    You are running traces underneath the gate drivers which reduces the isolation on your devices.  You NEVER run anything under a device which provides electrical isolation.  Often times you'll see slots cut in the PCB to aid in isolation. What you should see on your board if you hold it up to the light is opaque spots where your power pass section, translucent spots where your isolation barrier is.

To answer your questions:
A higher value gate resistor will increase the rise/fall time.  Your ringing is really bad.  Slow your switching time down to 800ns and see how that changes the ringing and overshoot. General rule of thums is you only switch as fast as you need to.  If I'm reading it correctly your +20V overshooting after turn off on a 48V DC bus.  No good.  Ringing = making noise= the enemy.  You should not need any snubbers for this project other than something like a 1-5uF polypropylene cap on your bus as close to the switching devices as possible.  Your DC link caps should not have any leads showing due to inductance.  Best type of cap for DC link is polypropylene, but enough electrolytics will get the job done if you don't care about cap life or have low ripple current.

To make measurements, use a probe holder of some sort and this type of lead if possible

  Make your own ground leads like this out of solid copper wire and solder them in the place you want to measure.  Short leads is the key.  If you have access to differential probes, use those, they make life so much easier.

You should consider also use 2 different bypass capacitor values 10/100nF on the gate drive power pins as close as possible to the driver chip.  A larger 10uF ceramic cap would also help with instantaneous current demand.

If you want to really learn this stuff, study Maxwell's equations and think about the physics at play.
This video does a good job illustrating the physics.

Thanks for your help.

I have watched the video and it does put help put thing into perspective, I will make sure to not run traces between ICs with Isolation on my final version. A 4 layer board should help with that.

I have differential probes at my uni and I will use them to take my final measurements.

You want to use different sized bypass capacitors to help with the frequency response as different sized caps will have a different impedance that will vary with the frequency you are running right?

With regards to current sensing are hall effect sensors such as the ACS712 and similar good for this application as a dense board layout might introduce more noise into the system. I want to use these since they have isolation built in and with a regular shut Id have to get an isolated op amp otherwise I'd lose my isolation.

Thanks!

[Glenn0010]

You may be aware of it already, but this blog:


http://scolton.blogspot.co.uk/p/motor-controllers.html

by Shane Colton covers a wealth of "DIY" motor controller design and experimentation!

Oh my!,

That is a gold mine and I was not aware of that. I will start reading up on his thesis as it seems like a great source to learn from.

I have seen those mosfet modules before such as the MTI 85W100GC. Should I go for one of them in the final board for compact design or should I go for discrete Mosfets. Also they do come with that copper plate on the bottom correct for heatsinking as it is not clear in the datasheet!

[Glenn0010]

Update:

So when I looked at my set up all of the stuff you guys said about inductance came into my mind and I was horrified! So I cleaned up some of my connections and saw an immediate improvement to my load spike voltage. It dropped form 70V to less than 60V. It could be down to the fact of improved load connections or improved probe connections.

I also added a 100nF ceramic capacitor across each half bridge and it made a huge difference.



Here are the difference the capacitor made:



The previous voltage spike was almost 60V and now the voltage spike is barely over 48V! So that is a huge improvment!!

I also got the results below. I was testing what effect the turn off  diode in parallel with the gate resistor would have. I do not know really how to interpret these results. Across Vgs of the High side FET the diode actually makes things worse as it introduces quite a bad negative voltage transient. Across the resistive load, there is no noticeable difference. This leads me to think I could do without this diode as it makes things worse across Vgs and has no effect on the load and it would save space and cost at the PCB.  I do not think it should effect an inductive load, since there is no difference in the resitive load. Is this a good assumption?





Any thoughts?

[Siwastaja]

Any thoughts?

You understood the issue, learned quickly, processed that information and found out how to improve it, and actually measured your success in no time. I'm sure you'll be a great power electronics designer sooner than many would expect seeing the first layout.