Best logic way to do this...

[alank2]

I'm thinking of picking back up an older project where I was connecting a Z80 to an AVR and using the AVR to handle the I/O so it will need to handle IN and OUT instructions.

My original plan was using a 74 flip flop that would assert the /WAIT line under the right conditions and then the AVR would notice the FF is set and handle the operation before clearing the flip flop and deasserting /WAIT.  Originally I was going to use a 138 to trigger the flip flop by G1=A7, A=A6, B=A5, C=A4, G2A#=IORQ#, G2B#=FFCLEAR so that it would trigger the flip flop on any IN/OUT of 0xF0-0xFF as long as the /FFCLEAR was not asserted.  This would allow the flip flop to be triggered (asserting /WAIT), but then allow me to to clear the flip flop even while /IORQ is still asserted.

Now I am simplifying and the AVR is the only I/O device, so I don't need to trigger on 0xF0-0FF any longer, any IN/OUT instruction should trigger.  So basically I want to assert /WAIT when IORQ becomes asserted SO LONG AS ffclear is not asserted.  I also thought, if IORQ isn't asserting on a low condition, but rather a transition from high to low, then I don't need to worry about the ffclear keeping it from retriggering the flip flop as it would only trigger the flip flop on a low going transition which will be later in another Z80 instruction.

Maybe I don't need a flip flop at all but some other type of logic.  Basically I need to let the low going transition of IORQ assert WAIT, and I need a way to reset WAIT that might happen while IORQ may or may not still be low.  Any thoughts on the lowest part count easiest way to do that?  I remember thinking that I could feed the IORQ into the CLK line of the 7474 and perhaps use that as a way to make it trigger only on a high to low transition.

[maginnovision]

On my old AVR proto doing something similar I used a small CPLD.

[nick_d]

We did something like this to connect a printer controller to a Z80 back in the day. The design was derived from an earlier design which used Epson's LA-180 dedicated printer controller chip, we basically replaced the expensive LA-180 with a cheap OTP micro and no software change as the micro was programmed to emulate the LA-180 in most respects.

Thing is that although the LA-180 looked like an 8-bit bus peripheral from the Z80's point of view, it really wasn't internally. I think Epson created it by basically mask-programming a generic micro, the same way as in our solution.

They had dealt with the problem you mention, by adding one level of buffering. That is, they'd created an 8 bit output port that could be written by the Z80 at any time and would retain its last written value. This could then be read by the LA-180's micro at any convenient later time. Once this had happened, the LA-180 would assert an ACK signal saying the Z80 could write the next byte. We connected this to a Z80 interrupt.

I think in our cheap OTP based micro version we added an 8 bit latch such as a 74HC573 to perform the latching function that was originally internal to the LA-180. (Epson's solution may have been based on a mask programmed micro, but if so they were able to add the latch internally for reduced parts count).

In a still later version of the system we used a Z180 not Z80 and we used the Z180's internal half-duplex SPI master controller to send data to the printer, by that time we were using an AVR as the LA-180 replacement instead of the original COP8SAC7 OTP micro, since a simple re-flash of the AVR could implement international character sets. Indeed we connected the Z180 to the programming pins and RESET of the AVR so that this could some day be done remotely, but such capability was never implemented unfortunately.

You should definitely look at the Z180, as the non multiplexed bus is much easier than the Z80's multiplexed bus.

cheers, Nick

[alank2]

maginnovision:  I want to try to use an offself the logic IC instead of a CPLD, but I appreciate the tip.

nick_d:  Your idea sounds cool because it doesn't hold up the Z80 I think.

I am thinking that a 74HC73 might work as a single IC solution:

/R will reset it taking /Q high again which goes to Z80 /WAIT
J=high
K=low
/CP will on a transition to low will take /Q low which goes to the Z80 /WAIT

[netdudeuk]

I'm thinking of picking back up an older project where I was connecting a Z80 to an AVR and using the AVR to handle the I/O so it will need to handle IN and OUT instructions.

My original plan was using a 74 flip flop that would assert the /WAIT line under the right conditions and then the AVR would notice the FF is set and handle the operation before clearing the flip flop and deasserting /WAIT.  Originally I was going to use a 138 to trigger the flip flop by G1=A7, A=A6, B=A5, C=A4, G2A#=IORQ#, G2B#=FFCLEAR so that it would trigger the flip flop on any IN/OUT of 0xF0-0xFF as long as the /FFCLEAR was not asserted.  This would allow the flip flop to be triggered (asserting /WAIT), but then allow me to to clear the flip flop even while /IORQ is still asserted.

Now I am simplifying and the AVR is the only I/O device, so I don't need to trigger on 0xF0-0FF any longer, any IN/OUT instruction should trigger.  So basically I want to assert /WAIT when IORQ becomes asserted SO LONG AS ffclear is not asserted.  I also thought, if IORQ isn't asserting on a low condition, but rather a transition from high to low, then I don't need to worry about the ffclear keeping it from retriggering the flip flop as it would only trigger the flip flop on a low going transition which will be later in another Z80 instruction.

Maybe I don't need a flip flop at all but some other type of logic.  Basically I need to let the low going transition of IORQ assert WAIT, and I need a way to reset WAIT that might happen while IORQ may or may not still be low.  Any thoughts on the lowest part count easiest way to do that?  I remember thinking that I could feed the IORQ into the CLK line of the 7474 and perhaps use that as a way to make it trigger only on a high to low transition.

I've already done something this -

https://www.eevblog.com/forum/beginners/flip-flop-frustration/msg339616/#msg339616

https://hackaday.io/project/182-z80-microcomputer

[alank2]

Did you use the 74 flip flop?  Did you end up configuring it so that a high to low transition of IORQ was the trigger?  Or just any low?  And if any low, how did you deal with clearing the flip flop while the IORQ is still asserted?

[netdudeuk]

Did you use the 74 flip flop?  Did you end up configuring it so that a high to low transition of IORQ was the trigger?  Or just any low?  And if any low, how did you deal with clearing the flip flop while the IORQ is still asserted?

Have a look at the first link.  Schematic and code in there