Author Topic: Capacitor paralleling, layout any best practices ?  (Read 1312 times)

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Offline MiyukiTopic starter

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Capacitor paralleling, layout any best practices ?
« on: September 25, 2018, 07:34:05 pm »
Hi folks,

if I need parallel capacitors to share ripple current

For example boost converter at 100kHz will need 3 big capacitors 35mm diameter
How to lay them when it is big parts and will take large area
Or just pour power planes and keep calm ?
 

Offline T3sl4co1l

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Re: Capacitor paralleling, layout any best practices ?
« Reply #1 on: September 25, 2018, 07:38:10 pm »
If they are right beside each other and you have both sides available for a pour, no problem, go for it.

Sharing isn't much of a problem for electrolytics, either.  It can be a concern for film and ceramic, which have much lower ESR.  In that case, use minimum stray inductance between parts (parallel plate transmission line, short distance between plates, wide cross section), and preferably connect to them evenly (similar distance from current source to each part).

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Offline GadgetBoy

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Re: Capacitor paralleling, layout any best practices ?
« Reply #2 on: September 25, 2018, 07:40:41 pm »
Only advice I can tender would be keep the leads short if you're running at a high voltage, and give the caps room to breathe so they don't overheat.

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Offline basinstreetdesign

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Re: Capacitor paralleling, layout any best practices ?
« Reply #3 on: September 26, 2018, 01:27:42 am »
Power planes are good, very good.  Just keep them close together, very close to the customer of the current delivered to or from.  Also I think it would be a good idea to put in parallel a smaller-valued cap or two on the side of the caps facing said customer, to make sure the ESR is kept low.  Depending on how much power you are moving, of course.
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Offline MiyukiTopic starter

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Re: Capacitor paralleling, layout any best practices ?
« Reply #4 on: October 04, 2018, 08:25:35 am »
And what about paralleling Film Capacitors ?

They have that big rectangular shape with leads far away (like that 22.5mm)
For example if I want to use three of them to share 10A ripple is ok to just put them next to each other on power planes ?

I can get Epcos/TDK ones for better price than electrolytic equivalent (same ripple current value)   
 

Offline T3sl4co1l

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Re: Capacitor paralleling, layout any best practices ?
« Reply #5 on: October 04, 2018, 04:58:40 pm »
Yes, usually okay.

Tim
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Offline coppercone2

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Re: Capacitor paralleling, layout any best practices ?
« Reply #6 on: October 04, 2018, 07:51:41 pm »
I made a giant mica capacitor out of a bunch of medium sized HVish paralell mica capacitors sandwiched between two sheets of copper. Must be over 100 capacitors I found in a trash one day, 11nF each.. mostly useless

I drilled alot of holes in two copper sheets that were lined up (fairly thick, maybe 1mm) and sandwiched the capacitors between them and bend the leads and soldered them from both sides. Was meant to be a HV tank for some experiment with a induction heater or other tuned oscillator circuits hooked up to fast  IGBT

If I connect the LCR meter to it, the de-5000, I get messed up readings depending on where I put the probes on the copper sheets (its like 5x3 inches or 6x3 inches). There is a effect of the sheet inductance. I was not sure why, or if my meter had low batteries, but I saw industrial literature that showed for large tanks, to make the capacitors with a specific shape of the bus bar..

http://www.celem.com/page.aspx?id=21&hmenu=37

scroll down to see whats going on.

it seems that for proper performance in high current applications you need to isolate the capacitors from the coil by some value of bus bar/sheet that is bigger then the interconnect area between the capacitors to ensure sharing. I think the over all impedance is higher but you get equal sharing. It depends what your looking to do.

I set it up like diagram A in that website because I did not know any better. It needs to be like diagram B or C for current sharing. The center bus bar in diagram C is about 30% wider then the bus bars over the capacitor terminals from what I can see.
« Last Edit: October 04, 2018, 08:02:36 pm by coppercone2 »
 


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