Chinese LCR meter schematic with STM32 questions, can someone translate please?

[Yansi]

Hello,
my friend is learning STM32 microcontrollers and wants to build a sort-of impedance analyser. As for an inspiration, I have come across this schematic. Unfortunatelly, I can't fully figure out what are some blocks doing.

As the F103C8 microcontroller doesn't have a DAC, pins PA6 and PA7 will somehow generate a sinewave. Does anyone know exactly how those pins are used? (But thats the lesser problem, my friend wants to use STM32 with DAC as a DDS generator - he has it already working). I'm just curious how the chinese guys got over with the PA6,7 pins.

The most mysterious block is the one bottom right, the two opamps. The first one looks like some sort of diff. amp. controlled by the PA0 and PA1 pins. What are these pins used for and what does the opamp do there? Can someone please translate the chinese labels near the MCU on the schematic?

And what is the use for pin PB6? It is labeled as 20kHz, but what does that mean?

How is the synchronisation done in this circuit? As I know, impedance vector analysis requires two signals: Reference and the measured one. Where does it get the synchronization from, so that it is able to integrate correctly the in phase or quadrature components?

Or is it just synchronized by the PA6 (PA7) pins that generate the waveform, and the additional phase shift by the filter is then canceled out by calibration of the device?



Thank you
Yan & my friend Mrkev

[albert22]

The most mysterious block is the one bottom right, the two opamps.

The two amps. form the synchronous detector. PA0 and PA1 are the reference squarewaves to measure the in phase and quadrature components. Basically the signal to be measured is multiplied by a squarewave and then integrated then sampled by the ADC of the uController.
PB6 is used to inject an uncorrelated (noise) signal to the ADC and then oversample to increase the resolution of the analog to digital conversion.
See here  http://kripton2035.free.fr/Resources/rlc2_english.pdf
for a more detailed theory of operation of a similar project (although some terms are in russian instead of chineese)

[Yansi]

So it really is, what I have thought it is. A switched polarity amplifier. So the circuit is quite stupid then.  I recommended my friend to make the synchronous detection in software, by multiplying the signal by sinewave and also integrating in software. Should get much more precision, shouldn't it?

Thank you for your answer, was very helpful and exactly what was needed. 

Yan

PS: Russian is not much of a problem...

PPS: One thing still bothers me... The pins PA0, 1 are configured as opendrain (most probably). The signal doesn't swing under 0V level or... ?

PPPS: Still a great construction, reasonable measurement qualities!

[albert22]

You are welcome.
There is an LCR meter project at Elektor:
https://www.eevblog.com/forum/testgear/500-ppm-lcr-meter-at-elektor-march-2013/
IIRC they sample the signal and then do the synch detection in the software.
I guess that configuring OD allows to multiply the signal by 1 or 0, so it makes sense.

[Yansi]

Hi again! Sorry for the delay,  been quite busy. Finaly got some time for my hobby during the Chrismyth ( ) vacation...

Thank you for the translation. 

Seems like the guess with opendrains was right. But how does it work? The ouput FET in the MCU cannot work with negative voltages (the substrate diode would conduct). So the signal voltages on these pins has to be small enough (<300mV I guess). And maybe that guess is also near enough, as there is some gain that suggest small voltage in the 0.1V range. That might work. Strange but maybe it is like that.

As I understand, the first opamp down there is a switched polarity amplifier. The PA0, PA1 pins grounds one or the other input, thus changes the polarity of the amplifier (like a multiplying detector). The only strange is, that also the gain changes. If PA0 grounded (PA1 floating), then the gain of the stage is (1+100k/51k) * 100k/(10k+51k+100k) = 1.83, and when PA1 grounded (PA0 floaing), the gain is as follows: -100k/(51k+10k) = -1.63. Isn't it an issue, that the detector is asymetric in gain?

I have studied also a few of those similar schematics. Very nice ideas. I have already put such LCR meter on my wish list what to do, if it happens I don't know what to do else first :-)

Thank you for help,
Yan

//EDIT: May I ask you please to translate also this one?

[Kleinstein]

For a small voltage (e.g. +-400 mV) an open drain digital output can be used as a switch to ground. For the syscronous detector it is not really important to have same amplificaion in both phases, it just would be better - but leaving some of the input signal is not changing the DC output. One can guess the amplitude from the level at the ADC and the amplification after the PSD.

I also find this circuit strange: the amplification is rather complicated with lots of OPs. As the ARMs have quite powerfull ADCs they could have better done the detection in software - it easier and likely higher quality. At least you get the phase and amplitude together and thus need only half the time.

[Yansi]

I hope my friend will not be angry at me, if I publish his results.

He's currently designing and impedance analyser (proportionaly variable measurement frequency) for an ultrasonic transducer as a part of his master's thesis. The current setup looks something like this:

An STM32F429i-DISCO kit as a processing base. DAC set as an 1Msps 12bit DDS (up to 100kHz output). Two ADCs for sampling (1MSps 12bit too) both current (from the I/V stage) and voltage at the same time. The phase detection is done therefore in software, by multiplying the sampled V and I components by sine and cosine waveforms, then integrated.

The sampled data are gathered into a buffer of 4K samples, processed after (real time should be pretty possible I think, but not implemented yet) in a float32. (Here comes the FPU really handy!)

The hardware is a simplified version of the first schematic in this thread, fixed gains (no MUXes present).

Only few test has been done so far, but results look very promissing. The 4K buffer is equal to about 4.1ms of integration (at 1MSps). The values are quite stable, 4 significant digits holding. I have suggested him to integrate for a multiple of 20ms, to supress mains related noise.
Here is a short sampleset of data measured with a 56ohm resistor as a DUT. First column is resistance in hundred ohms, second column is phase angle in rads. No calibration whatsoever, only raw acquisition, if I remember right.

Code: [Select]

R: 0.564495 -0.034469
R: 0.564533 -0.034413
R: 0.564518 -0.034521
R: 0.564587 -0.034505
R: 0.564587 -0.034476
R: 0.564461 -0.034459
R: 0.564528 -0.034473
R: 0.564542 -0.034463
R: 0.564460 -0.034557
R: 0.564542 -0.034640
R: 0.564416 -0.034613
R: 0.564459 -0.034654
R: 0.564485 -0.034441
R: 0.564364 -0.034402
R: 0.564459 -0.034538
R: 0.564481 -0.034526
R: 0.564404 -0.034598
R: 0.564456 -0.034624
R: 0.564460 -0.034646
R: 0.564430 -0.034714
R: 0.564458 -0.034628

I will ask my friend if he is willing to share some photos of his prototype :-)

I am quite interested in his work, as I plan for many years to build myself a decent LCR meter and finaly got some ideas for a real one. Happy to see any improvments in his work.

So what do you guys think, any suggestion how to make it even better? :-)

Yan

[Chen Li]

Basically four leads kelvin connevtion, three discrete adc incorate to one instrument adc, one signal generator.