Common mode choke off the power supply PCB is better?

[ocset]

Thankyou, that was very enlighteing, so if live and neutral conducted emissions scans are different, then that means its a mixture of common mode and diff mode emissions?
Presumably, the more different they are, the more it means ....urmm...something (?)

[ocset]

Also, this is a related post (concerns the same PCB), so please may i add it here, it saves putting lots of different posts up?...

Hello,
Please  help us to pass conducted emissions of EMC testing, particularly with reference to common mode noise created by the switching node of our 1W Buck converter
We have  a 1W Buck converter  (bias supply) on our offline 150W  LED driver PCB (which uses  linear  current regulators).
It  firstly failed EMC due to having the Buck’s switching node copper layed out all over the bottom PCB layer, where it was  next to the earthed heatsink. (common mode emissions).
We now have  removed the switching node copper from the bottom layer. However, do you believe that we should shield the switching node copper (which is now only on the top layer) from the earthed heatsink   by putting some “quiet node” copper underneath the switching node of the Buck, in order to shield the switching node from the earthed heatsink on which the PCB sits?
(eg we could put the “quiet node copper” on middle  and bottom layers of the 4 layer board. The switching node copper is now only on the top layer. The PCB sits on a thin thermal pad which is on the earthed heatsink)

[Phoenix]

Thankyou, that was very enlighteing, so if live and neutral conducted emissions scans are different, then that means its a mixture of common mode and diff mode emissions?
Presumably, the more different they are, the more it means ....urmm...something (?)

Yeah that's about the gist of it.

You can start looking at RF combiners - very useful if you understand what's going on. Great way to generate confusion if you don't. Keep in mind that subtracting two signals that are in phase is the same as adding two signals that are 180deg out of phase.

0 degree combiner - adds signals A + B
- Any signal only in A or B only will pass through at +0dB.
- Any signal which is common to both A and B will sum together at +6dB (double the magnitude).
- Any signal which is 180deg out of phase will sum to zero.
Any signal that increases when using a 0deg combiner is a good sign it's common mode. Conversely, any signal that reduces is differential mode.

180 degree combiner - subtracts signals A - B (doesn't matter which one is subtracted).
- Any signal only in A or B only will pass through at +0dB.
- Any signal which is common to both A and B will subtract to zero.
- Any signal which is 180deg out of phase will sum together at +6dB (double the magnitude).
Any signal that increases when using a 180deg combiner is a good sign it's differential mode. Conversely, any signal that reduces is common mode.

[ocset]

Thanks,
The offending switching node is as in the attached....

Attached please find the PCB area containing the HV DC Buck converter and the switching node.
I wonder if it would be worth adding a small “metal box”  kind of like a tent (a shield) above the switching node copper, the inductor and diode? Maybe this would stop the radiation from eminating out from the switching node and going into the earthed heatsink? We could solder the box to a quiet node on the PCB? This would reduce common mode emissions?

[T3sl4co1l]

Seems like a missed opportunity, not putting ground pour beneath the offending area.  Shunting that capacitance to ground, at the source, will be a whole lot better than doing it through a Y cap, or with additional filtering!

Tim

[dmills]

Also, the area of that switching node is WAY larger then it needs to be just in terms of polygon area.
You almost always want to minimise stray capacitance from these nodes so making that a reasonably thin track seems likely a better design then using a polygon here.

I might try a quiet node under it but that is tricky, and would be a copper tape sort of experiment rather then having a board made.

Are the internal layers kept away from that node?

Regards, Dan.

[Phoenix]

I might try a quiet node under it but that is tricky, and would be a copper tape sort of experiment rather then having a board made.

Very thin copper sheet with a layer of kapton tape on both sides to insulate, connect it to the GND node. Seems like a good idea and a fairly straight forward experiment.

Is that polygon area required for heat sinking?

[ocset]

Are the internal layers kept away from that node?

Thanks, yes, we unfortunately put no copper planes  directly beneath the switching node.

Is that polygon area required for heat sinking?

Yes, thats why we didnt really massively minimise it

Very thin copper sheet with a layer of kapton tape on both sides to insulate, connect it to the GND node. Seems like a good idea and a fairly straight forward experiment.

Thanks, d'you think the experiment is needed?, i mean, i thought it was a cast iron certainty that shielding high dv/dt nodes with a quiet circuit node was a gauranteed winner? (ie putting a copper planes beneath the switching node on layers 2,3,4(bottom))

[dmills]

Adding a shielding plane raises capacitance and changes the ringing frequency and level however, so it might solve this only to pop up a problem someplace else.
If you are going to do it, I would suggest the bottom of the board rather then layer 2.

Regards, Dan.

[ocset]

Adding a shielding plane raises capacitance and changes the ringing frequency and level however, so it might solve this only to pop up a problem someplace else.
If you are going to do it, I would suggest the bottom of the board rather then layer 2.

Thanks,  though surely if the shield layer was on the bottom of the pcb then that is going to increase the capacitance to the earthed heatsink that the pcb sits on?. ....and we thought it was such capacitive coupling which causes common mode noise?...so surely we would be better off putting the shield layer directly under the switching node?...ie on the 2nd layer down on the pcb?

[dmills]

Trade off, and in any case your shield is hopefully connected to a quiet node so it should not be radiating to the heatsink, this being rather the point.

The issue is that you are adding capacitance to a node running at MHz plus harmonics rates and that is usually not a happymaking thing, minimising the capacitance will both reduce the impact on the switching node and reduce the current flowing in the resulting loop.

Regards, Dan. 

[ocset]

Thanks, i must admit i respect, value and appreciate all replies here. Some of them seem to contradict each other. I am now not at all sure whether its worth us adding a shielding layer under the switching node at all...even if it is connected to "quiet node" copper.

[jbb]

Thanks, i must admit i respect, value and appreciate all replies here. Some of them seem to contradict each other. I am now not at all sure whether its worth us adding a shielding layer under the switching node at all...even if it is connected to "quiet node" copper.

Yep, that's EMC for you.  It does all follow Maxwell's Equations, it's not really magic, but the small details can be really important.

In this case, copper tape - connected to the appropriate point! - might be effective by shunting stray capacitive currents back into the ground plane.  You will end up with more stray capacitance, and this will have a (hopefully) small impact on the converter losses. If you connect the tape to the wrong node it might even make the EMI worse, but you won't know unless you a) try or b) go crazy with some really expensive simulation tools.  This is why copper tape is a thing - you can try it out without spinning new boards.

And once again, we see that a cheap LISN + spectrum analyser could be useful.  It won't be accurate, but it can answer questions like 'is this better or worse.'

[dmills]

A bit of copper tape, some Kapton, and a little quality time with a spectrum analyser should answer this within an hour or so and the answer will be right for your specific case.

I would note that the reason you are getting seemingly contradictory answers is that all engineering is the art of the tradeoff with incomplete data, and particularly with this sort of thing you may not know the parasitics well enough to know what trades you are making, sometimes you just got to experiment.

We also have incomplete data so all any of us can do is throw ideas out there, up to you to do the experiments that prove or disprove particular possibilities being relevant to your specific case.

The alternative approach is the 2.5 or 3D electromagnetics solver, useful when designing 10GHz and up transitions on FR4 but just doing the experiments is cheaper for most mundane stuff. 

regards, Dan.

[Ghydda]

Some of them seem to contradict each other. I am now not at all sure whether its worth us adding a shielding layer under the switching node at all...even if it is connected to "quiet node" copper.

And you would be right. But as you might have discovered by now, any attempt to mitigate EMI has a penalty. Knowing the ratio of the penalty vs. gain determines whether you should implement it or not. This is usually done by trial and error tests.

That is why nobody on a forum can make definite suggestions for your design, but rather make observations and try to link them to possible causes and remedies.

It is frustrating, especially when EMC seems like pure voodoo and witchcraft.

But as everybody says, minimize loop areas and minimize stray capacitance all leads to lowering the amplitude out of your EMI-generator, making the life of the filters easier. This must be balanced against adequate cooling for your power semiconductors. Not an easy feat.

I would consider reducing the cooling are on top and go for a secondary cooling copper pour on the inner layer just below it, which should be tied to a quiet reference point.
If the top layer and the next one is spaced very closely in the board stackup, then you can achieve adequate cooling performance IMHO.


Best of luck.



Cheers!

[T3sl4co1l]

Thanks, i must admit i respect, value and appreciate all replies here. Some of them seem to contradict each other.

Like I said, misinformation abounds.  Nobody does the analysis, even though they can easily do it.

But what do you expect, you get what you paid for.

If you want to pay me for my opinion, I'd be glad to write it down in PDF format for you.

Tim

[jbb]

Absolutely.  It's well known that PDF format makes all technical reports more accurate

[ocset]

I would suggest that the earthed heatsink is probably not doing you any favours for common mode, a class Y cap or two between some carefully selected points on the PCB and the heatsink mounting screws would probably help by providing a return path for capacitive coupling.

(from Reply #21)

The problem in smps is nodes with very high dv/dt capacitively coupling larger currents to (I=C dv/dt) to ground. The only return path is through the cord. Adding a Y cap from an appropriate electrically quiet node (eg a dc bus rail) to the heatsink gives it a return path.

(from Reply #23)

Current wants to couple from the switching nodes into the heatsink via the nice large flat transistor surfaces. This current needs to have a return path somewhere:
Your device -> Heatsink -> earth lead -> LISN (250 nF, 50 Ohm) -> active and neutral -> Your device

Adding Y caps from the heatsink to a select node short circuits the LISN path:
Your device -> Heatsink -> Y capacitor -> Your device
But also opens up the new current path:
Your device -> Y capacitor -> Heatsink -> earth lead -> LISN (250 nF, 50 Ohm) -> active and neutral -> Your device
So you need to chose your nodes carefully!

(from Reply #25)

**Y capacitors force conducted EMI from the load side back into earth, away from the mains.
I think this is about using Y caps in your CLC. The abstract theory is they allow the common mode currents to return back into your device without going via the LISN - effectively the same current paths as I described earlier, but different node on your device.

From Reply #25



Thanks, all these posts seem to point to the fact that Y capacitors are not actually used as  part of an LC filter to filter common mode noise, but instead, they simply act as “bridges”  across which noise can come back into the device without going through the LISN. Is this true, I previously thought that Y capacitors act in LC filters along  with the common mode inductance?

So Y capacitors are not used in "filtration", but instead are used to "invite" noise that has coupled out into the earthed heatsink to couple back into the product, without going through the LISN. Is this true?

[dmills]

They are used in the same modes that any other cap is used, filters & coupling mostly.
It is seldom particularly meaningful to think of components purpose in isolation, instead you need to think of the circuit formed.

Regards, Dan.

[ocset]

Thanks, but adding Y caps from earthed heatsink to a circuit is surely a specific case all of its own?. It involves the capacitor basically providing a "short circuit" to emissions so that they can be diverted back in to the circuit instead of going back through the LISN, where they can cause common mode emissions and invite regulatory penalisation.  This is different to a Y capacitor at the mains inlet to a circuit, which does indeed attenuate common mode emissions by acting as part of an LC filter with the common mode choke.

There are thus 2 distinct uses of Y capacitors in combatting common mode noise.....
1...In "filtration" (attenuation of the common mode noise)
2....In "diversion".....diverting  emissions away from the LISN so that they can't be detected as common mode noise.

[T3sl4co1l]

Er, why are those exclusive?

They do all three.

Tim

[ocset]

Thanks but surely "diverting" emissions back from an earthed heatink , back into the circuit from which they emanated, so as to avoid them going through the LISN is not "filtering"...but is a case of  "diverting"...these are exclusive actions, surely?

[T3sl4co1l]

It's attenuating a high frequency signal, how is that not filtering?

Tim

[Ghydda]

Thanks but surely "diverting" emissions back from an earthed heatink , back into the circuit from which they emanated, so as to avoid them going through the LISN is not "filtering"...but is a case of  "diverting"...these are exclusive actions, surely?

The mains wiring to your device is an antenna. If it carries lots of high frequency current, then you will radiate substancial amounts of RF-energy into other neighbouring electrical systems. We do not want that.

That is why stopping/diverting the RF-current before it reaches the LISN is an excellent idea.

You _will_ have undesired current flowing in your switch mode design. It is unavoidable because physics. Just don't let that current flow on your antennas and all will be good.

The goal is not to eliminate high frequency currents, but rather control where it flows, so that it will not become a big transmitter. That can be achieved by filtering (which is just another word for current diversion in this context) and/or by reducing the generator amplitude. Usually a combination of both is required to meet regulations.

Cheers!

[Phoenix]

Thanks but surely "diverting" emissions back from an earthed heatink , back into the circuit from which they emanated, so as to avoid them going through the LISN is not "filtering"...but is a case of  "diverting"...these are exclusive actions, surely?

"Filtering" is a high level concept - good for explaining to management why you're adding Y caps but gives no insight into why it is doing something.
"Diverting currents" is a more circuit level concept which comes from the circuit analysis you should be doing.

They are the same thing from a different perspective.