FYI, Q4 gate is coming out the wrong side (note on Q1, it's drawn exiting from the source side). Also, BSS84 would be more traditional there, though it won't make any difference if you don't mind the extra capacity of the IRLML2246.
If you want a more accurate near-zero threshold for IC4, you can replace R53 with a pair of resistors to GND. This anchors the middle of the divider (indeed, splits it into two separate dividers), so that ratio differences in R50/R55 have less effect.
Also, the output resistors as chosen (R48, R49, R54, R56) are such that D12, D13 don't do anything. The diodes might be relevant if the supplies come up at different rates (though, within ratings, the MOSFETs will never be in danger). Or if you want to make use of them, it would be perfectly fine to reduce the resistor ratios, so that the diodes become forward biased while the comparators are on. Really doesn't matter, it's very mildly redundant.
(I guess what I'm feeling, philosophically, is: if you have the choice between two nearly equivalent options, you must be near -- but not on -- a local minima; this is a sign that you perhaps should rethink the thing, until you find an even better local (perhaps even global) minima. At least, when it's something that's actually worth the work.)
The voltage compensation (around IC1) seems odd. There's a mess of lead-lag compensation (C4-C7, C9, C10), which seems to suggest you're trying to beat causality. Which is impossible, of course. A resistor in series with C8 would help (some pole-zero action, presumably to cancel a different pole, maybe that due to Q1's gate capacitance?), and probably slowing down the whole thing so it's not so much on the knife-edge of stability.
It also wouldn't hurt to have some raw C-to-ground on those feedback nodes, just to take the edge off.
Which segues into the other filter thing: the shunt sense IC3 should have some filtering on its inputs. This is a bipolar op-amp, at very small signal levels, so it will be doubly important to keep HF noise (anything over perhaps 500kHz) well away from it. R35, R38 are also rather low values, which are something of a fault hazard to IC3 -- short circuit current through the shunt can deliver quite a bit of current into the IC's input protection diodes. I'd suggest >100 ohms, perhaps split in half (2 x 51 ohm each?) with a 4.7nF to ground (in the middle) for filtering.
IC1B should also have some filtering, for similar reasons: suppose you have a heavy, nasty switching load connected to this thing (maybe it's an unfiltered DC-DC converter drawing nasty current spikes, or a high voltage generator spewing out common mode interference). That noise goes straight into your op-amps, which respond asymmetrically to RF inputs, resulting in shifted bias points and DC error. Now, TL071/2 is a FET amp, which is less susceptible to interference, but I'd still add a 1MHz or so LPF to be sure.
BTW, you might swap IC2 for 1/2 TL072, just to save a BOM item. The extra half can simply be grounded (+in = out, -in = GND).
Going back to IC1 and IC2, it seems rather odd to use +/-15V supplies, yet use only about the -2 to 0V range. You should use only as much as needed, so the outputs don't have to slew so far when they go into the linear range. This reduces integrator windup, which is a significant limitation on the speed of this type of control circuit. Simple solution is to increase R24 and/or R18 dramatically, so the gain is lower and the useful op-amp range is wider.
Alternately, you could rewrite much of the circuit to use, say, +/-5V supplies (which would eliminate one supply), and use a R2R type amp like TLV2372.
ZD2 seems kind of out of place. I don't like to see zener diodes chained in series with things, used as afterthoughts for burning voltage; it's a lazy method that often leads to problems arising from side effects. I'd just as well clamp Q6 collector to ground with another BAS316, which seems to be fine as it's already current limited. Also won't need D2, as D3 prevents backflow from anything else (Q2 and stuff are always below Q1 source, so aren't going to turn it on, ever).
The Q4 pulldown stuff seems odd (it's like Q1 and Q4 act as a complementary source follower pair), but I guess it's really only being used as a turn-off discharge. Beware that it won't operate very happily if you were charging a battery pack then hit the "disable" switch! (That said, 50V maximum and ~0.3A limit suggests a modest 16W maximum dissipation, which is fine for a TO-220 MOSFET like that. As long as you have the load current displayed, the user will be able to see their battery charge being pissed away, too.
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Note that Q5 can beat the shit out of Q1 gate (in the turning-on direction), but nothing is there to discharge it (just measly little R3). So you'll get the weird situation that, if it's on the verge of oscillation, it's able to rise much more quickly than it falls, and this can lead to weird load- or state-dependent compensation, and possibly chaotic behavior. A more symmetrical driver would clean that up, and also raise the cutoff frequency of that node, easing compensation for the gain stage (i.e., Q9 and related parts) and error amps.
Note that Q5 doesn't have a nearby bypass cap, which may make things ugly for that bias supply (I don't know what's plugged into it, a board-to-board or a cable or who knows).
Anyway, on to the PCB:
As mentioned, you've got tons of slots going vertically along the bottom ground pour, so all those traces crossing them on top (Q10, R27; and by extension, the power going up to IC1 -- note that the PSRR of an op-amp is more dominant than RF susceptibility!), as well as extending downward until those loops close up (so this includes injecting noise into C11-C12-C14 and IC3).
The power circuit makes a grand loop, from X1 around Q1-R1 down to X2, then back through R37, over split ground. If this circuit is exposed to ground loop current, it will feel every little bit of it in this loop here. The voltage sense amp is right there, which kind of sucks. Like I said, it's somewhat less sensitive, but it's still not desirable for accuracy.
Ideally, all the grounds (especially on connectors) should all be joined together, as closely as possible, thus minimizing ground loop areas, and keeping any ground loop currents away from your main circuit. This would require moving X1, X2 and R37 near each other, perhaps making the return path above Q1, Q4 (they could be changed to horizontal orientation, parallel to the board, installed on the bottom side but facing up, perhaps?), and moving the connectors somewhere up near a corner, or along the top edge.
I'm guessing the rest of the circuit isn't a big deal. X3 has some grounds, which might be worth looking out for (minimize possible ground loop areas!). I'm hardly concerned about SPI and digital; those are hiding in the corner, well away from the analog parts.
But you should follow much the same idea, for the analog part as well: so the small-signal parts (op-amps and all) are isolated in their own group, away from the power path (Q1, Q4 and etc.), to keep them out of the way of stray currents and such.
And, again: top side pour, and lots of stitching! For example, stitching over the slots in the ground pour (formed by the supply traces coming off X3 and running vertically for most of the board) just about eliminates that concern, so that the R37 path can be almost as good as the most suitable alternative (curving back above Q1, Q4). But avoiding signal and power trace crossings altogether is even better, so try for that first.
HTH,
Tim