Critique my design and PCB layout please!

[TimNJ]

Hi everyone,

I've been busy working on my EE senior design project which is a data acquisition system for biomedical signals, namely ECG and EEG. You may remember me asking a few questions regarding this a few months ago. Thank you for your contributions if you helped.

I'm on a three member team and I'm responsible for the hardware design. A pair of electrodes with a third reference electrode creates the differential signal which is amplified by an instrumentation amplifier, filtered, and converted to unipolar (0-3.3V) for our ADC. We are using an Arduino compatible Teensy 3.2 board which uses a Freescale MK0 MCU (ARM Cortex M4 core). The digitized data will be passed to a Adafruit ESP8266 HUZZAH board which will transmit the serial data to an Android device. To reduce capacitively coupled noise in the probes, we are driving the shield with the common mode voltage of the inputs. Similarly, to reduce common mode interference, we are using a right leg drive circuit (RLD). Due to their half-cell potential, typical Ag-AgCl electrodes can produce a DC offset of around 200mV so we implemented a circuit which removes this offset.

We are using an analog switch to toggle between the ECG and EEG range. Essentially just swaps a feedback resistor out. Each range has its own adjustment pot.

We are using two externally charged 18650 lithium cells. Since each cell could potentially be inserted in reverse, each cell gets its own reverse polarity protection MOSFET. (Does this work the way I'm intending??).

This is the first board I've ever laid out. It is 2 layers with the bottom layer as the ground plane. After routing the critical signal traces, I filled in most of the top layer with Vcc, and a small pour of Vee. Surrounding the input connectors and differential input signal, I poured the driven guard net to guard the signal up until it reaches the instrumentation amp. (Maybe?)

Well, if you have any ideas or suggestions, I am reaaally excited and happy to hear them. Thank you so much.

[T3sl4co1l]

No ground stitching?

[TimNJ]

No ground stitching?

I don't have a ground pour on the top side. Where would you expect/suggest to use ground stitching? Thanks.

[pitagoras]

1) Label the trimpots with their function? Place them "making sense", I mean not the 3 together as they control different things, also probably close to inputs if they control something related to inputs...
2) Add test points?
3) Not sure if there are enough dc decoupling caps for everything.

[TimNJ]

1) Label the trimpots with their function? Place them "making sense", I mean not the 3 together as they control different things, also probably close to inputs if they control something related to inputs...
2) Add test points?
3) Not sure if there are enough dc decoupling caps for everything.

Thank you.

1.) Good point, will definitely include silkscreen labels for each. If this was a real product, they would only be accessible to a person performing calibration.
2.) Yes, though I feel like probing some SO-8 pins/0805 parts won't be too hard. But always love equipment with proper test points.
3.) Do you mean bypass caps? There is one 100nF on each power pin of each IC.

Thanks again!

[T3sl4co1l]

No ground stitching?

I don't have a ground pour on the top side. Where would you expect/suggest to use ground stitching? Thanks.

But what's all that copper--

It isn't VCC, is it?  That's not a good way to go.  You have to stitch two planes that way, and you have no choice but to use via-track-via 'jumpers' to do it.

Or even worse, is it floating? 

The best starting point is N layers, of which N/2 layers dedicated to the highest pin-count nets (usually in order: GND, VCC, VEE, other supplies, shield nets, etc.), and N/2 are reserved for routing.  You can route traces on the plane layers, briefly, but try to keep the "jumper" lengths to a minimum.

All other nets, that aren't planes, are routed as any other signal.  Given suitable consideration for trace width, impedance, bypassing and so on.

For N=2, you should place and route everything on top, and reserve bottom for ground.  (Or vice versa is fine too, but you'll usually have SMT components on top, making that preferred for routing.  A THT design might route on the bottom, and fill the top with ground.)  VCC and everything else gets routed as traces.  You usually need more bypass caps on a 2-layer design than a 4-layer design; heck, a 4-layer design often needs no more than a handful of bypass caps, even for a complex design.

Obvious catch: inevitably, you'll need to route on the bottom, which will cut holes in the ground pour (you have to watch the negative space!).  To patch over these gaps, you'll need to add via-trace-via links, reserving enough space in your top-side routing to allow for it.  Better still, you can pour the top side, using all the negative space leftover from routing.  Just add vias!

Tim

[TimNJ]

No ground stitching?

I don't have a ground pour on the top side. Where would you expect/suggest to use ground stitching? Thanks.

But what's all that copper--

It isn't VCC, is it?  That's not a good way to go.  You have to stitch two planes that way, and you have no choice but to use via-track-via 'jumpers' to do it.

Or even worse, is it floating? 

The best starting point is N layers, of which N/2 layers dedicated to the highest pin-count nets (usually in order: GND, VCC, VEE, other supplies, shield nets, etc.), and N/2 are reserved for routing.  You can route traces on the plane layers, briefly, but try to keep the "jumper" lengths to a minimum.

All other nets, that aren't planes, are routed as any other signal.  Given suitable consideration for trace width, impedance, bypassing and so on.

For N=2, you should place and route everything on top, and reserve bottom for ground.  (Or vice versa is fine too, but you'll usually have SMT components on top, making that preferred for routing.  A THT design might route on the bottom, and fill the top with ground.)  VCC and everything else gets routed as traces.  You usually need more bypass caps on a 2-layer design than a 4-layer design; heck, a 4-layer design often needs no more than a handful of bypass caps, even for a complex design.

Obvious catch: inevitably, you'll need to route on the bottom, which will cut holes in the ground pour (you have to watch the negative space!).  To patch over these gaps, you'll need to add via-trace-via links, reserving enough space in your top-side routing to allow for it.  Better still, you can pour the top side, using all the negative space leftover from routing.  Just add vias!

Tim

Yeah that copper is Vcc and Vee. I can obviously convert all of those fills back to traces (they were at one point). I figured pouring Vcc and Vee would lower the impedance (series inductance) and would be a good thing. Is this bad from an EMC standpoint? I've seen this done..but I would like to know why it might be (is) bad. Are you suggesting to fill the top layer (whatever's left after routing signals and power) with GND? Better for conducted emissions..?

My bottom layer is completely ground minus two very short (0.2") jumpers. By floating, do you mean no planes at all? It is not that. Currently using 100nF ceramics for bypassing. There is one Vcc trace that is long compared to the rest so I might throw a 1uF or 10uF in parallel for that o ne. The range of frequencies of interest is like 0.3Hz to 150Hz. Not sure if that affects bypass cap requirements.

Thank you very much!

[TimNJ]

On a side note, I'm considering swapping out the BNCs for a single DB-9 connector and creating a small breakout box like the commercial options offer.



If anyone knows anything about driven shields and biomedical measurements...

The current design drives the shields of the 2 measurement cables with the common mode input voltage (to reduce leakage currents). The right leg drive cable's shield is connected to ground. Does anyone see a problem with bundling the all 3 of these wires together into one coax (basically a VGA cable) and driving its shield with the CM voltage? Thanks.

[T3sl4co1l]

Yeah that copper is Vcc and Vee. I can obviously convert all of those fills back to traces (they were at one point). I figured pouring Vcc and Vee would lower the impedance (series inductance) and would be a good thing. Is this bad from an EMC standpoint? I've seen this done..but I would like to know why it might be (is) bad. Are you suggesting to fill the top layer (whatever's left after routing signals and power) with GND? Better for conducted emissions..?

Ah.  Yeah-- that's not too bad if you've placed a bypass cap at every "peninsula" of Vcc (which, actually, would make the layout almost as good as a 4-layer board!), but it seems likely that there are a lot of those, and so, placing all that bypass would be more irritating than bypassing only where needed (at the ends of Vcc traces).

If you've done the one but not the other (i.e., bypass at pins, not at the tips of peninsulas), that's certainly still better than otherwise.  The downside is, you don't have any idea what kind of impedance and resonance that supply will have, unless you take a solid look at where all the copper is.  (And, as your layout changes in development, the negative space around that routing also changes, which means your Vcc network changes!)

Any cuts, slots, gaps, peninsulas, islands, stuff like that, are potential antennas.  From any such feature, you get a few peaks at high frequencies (where the wavelength is on par with the slot length or island perimeter), and an equivalent inductance at low frequencies.  If you have a lot of current (like a switching converter), the equivalent inductance will be important.

An antenna is symmetrically a receiver and a transmitter.  If your circuit is producing noise at frequencies where the antenna resonates, then that's an emissions problem.  If your circuit is sensitive to noise at frequencies where the antenna resonates, then that's a susceptibility problem.

The latter is probably the bigger concern (especially with a circuit that doesn't have any obvious super-high-frequency sources!).  Especially as RF can be rectified into DC offsets or AC crosstalk.

Have you ever had the experience of a sound system producing a "bip bip beep" sort of sound, just before receiving a text message or phone call?  Yeah, that's GSM radio being detected by a shitty analog circuit!



Even if the circuit isn't an emission or susceptibility problem, this is good practice for the cases when it is (anything switching, digital, high frequency, high sensitivity).  And making it better, even when it's not required, will still make the circuit strictly better (though maybe not by enough to measure..).

Tim

[ez24]

Interesting    

[TimNJ]

Yeah that copper is Vcc and Vee. I can obviously convert all of those fills back to traces (they were at one point). I figured pouring Vcc and Vee would lower the impedance (series inductance) and would be a good thing. Is this bad from an EMC standpoint? I've seen this done..but I would like to know why it might be (is) bad. Are you suggesting to fill the top layer (whatever's left after routing signals and power) with GND? Better for conducted emissions..?

Ah.  Yeah-- that's not too bad if you've placed a bypass cap at every "peninsula" of Vcc (which, actually, would make the layout almost as good as a 4-layer board!), but it seems likely that there are a lot of those, and so, placing all that bypass would be more irritating than bypassing only where needed (at the ends of Vcc traces).

If you've done the one but not the other (i.e., bypass at pins, not at the tips of peninsulas), that's certainly still better than otherwise.  The downside is, you don't have any idea what kind of impedance and resonance that supply will have, unless you take a solid look at where all the copper is.  (And, as your layout changes in development, the negative space around that routing also changes, which means your Vcc network changes!)

Any cuts, slots, gaps, peninsulas, islands, stuff like that, are potential antennas.  From any such feature, you get a few peaks at high frequencies (where the wavelength is on par with the slot length or island perimeter), and an equivalent inductance at low frequencies.  If you have a lot of current (like a switching converter), the equivalent inductance will be important.

An antenna is symmetrically a receiver and a transmitter.  If your circuit is producing noise at frequencies where the antenna resonates, then that's an emissions problem.  If your circuit is sensitive to noise at frequencies where the antenna resonates, then that's a susceptibility problem.

The latter is probably the bigger concern (especially with a circuit that doesn't have any obvious super-high-frequency sources!).  Especially as RF can be rectified into DC offsets or AC crosstalk.

Have you ever had the experience of a sound system producing a "bip bip beep" sort of sound, just before receiving a text message or phone call?  Yeah, that's GSM radio being detected by a shitty analog circuit!

Even if the circuit isn't an emission or susceptibility problem, this is good practice for the cases when it is (anything switching, digital, high frequency, high sensitivity).  And making it better, even when it's not required, will still make the circuit strictly better (though maybe not by enough to measure..).

Tim

Tim,

Thanks so much for all of your advice. I'm reworking the layout right now to get rid of all of those little antennas  . Just doing point to point with all of the power rails now. (Also made an executive decision to use one DB-9 instead of three BNCs for the sake of practicality. This is supposed to be a low cost device for developing countries and I don't think RG-316 patch cables are very cheap, plus the connectors..)

Regarding GSM interference, yes! I soldered together a DAC kit for my computer and while it sounds great usually, it's got a terrible "bip bip beep" problem.

Now, what will filling in the top layer with GND accomplish?

[T3sl4co1l]

Besides providing automatic jumpers for stitching vias, top-fill helps shield the top traces.  E&M coming in from the top side is more likely to hit ground than trace -- giving less induced voltage or current, for a given field.

A board designed this way is about as susceptible as a 4-layer board with internal planes.  (The internal planes being pretty close to the surface -- usually a depth of 7 to 15 mils -- provides the same effect.  The traces are also thinner for the same impedance, when controlled impedance routing is needed, which gives lower susceptibility.)

Tim

[TimNJ]

Besides providing automatic jumpers for stitching vias, top-fill helps shield the top traces.  E&M coming in from the top side is more likely to hit ground than trace -- giving less induced voltage or current, for a given field.

A board designed this way is about as susceptible as a 4-layer board with internal planes.  (The internal planes being pretty close to the surface -- usually a depth of 7 to 15 mils -- provides the same effect.  The traces are also thinner for the same impedance, when controlled impedance routing is needed, which gives lower susceptibility.)

Tim

Ahh...that makes sense. I've done my best to re-layout the board with all this is mind. I have via-ed from the bottom ground plane up to areas where ground couldn't reach on the top layer. Is that good practice? I haven't done any via stitching yet. Do peninsulas, stubs, etc. matter in the ground pour?

As always, thank you.

[T3sl4co1l]

You can connect a lot of those by moving traces around, to allow ground to pour around the vias and traces, like that X crossing there, and the stuff going up and under the right IC.  Think negative space!

Tim

[TimNJ]

Digging up this thread from about two months ago.

I made a bunch of design changes, dropping the coax inputs, one op amp, switching from a WiFi + MCU module to an Arduino MKR1000 all in one module, switched from 2x 18650 battery holder to 1x 18650. Also designed it to fit in a Serpac H67 enclosure (mounting holes not placed yet). Most of this was to bring down size and cost.

Here's the new PCB I came up with. Any thoughts or suggestions? I wanted to via stitch the whole board in a grid but KiCad doesn't seem very conducive to that.

Thanks!!

[amitchell]

Can you not set your grid spacing to say 100 to 200mils and just copy Vias using that spacing? That's how I do it in Eagle.