D-S voltage on MOSFET/IGBT rise is much faster than miller region?

[cjk2]

I have a two half bridges that run from a 400V bus. One half bridge is with IKW40N65F5, the other is with IPW65R110CFD.

On each transistor there is 30nH of added common source inductance in the form of a T25-52 bead. I also have a BLM41PG600SN1 ferrite bead on each gate. Gate drive resistance is 13 ohms in parallel with a diode for fast turn off and dv/dt induced turn on resistance. Gate drivers are Si8261BCC-C-IP.

Anyway, that is probably beside the point because my question/point for discussion is the following:

If my miller region (gate - source/emitter) is 100 ns long and decent looking, why does the drain - source/collector voltage swing so fast? I have see up to 60V/ns which is too high even for my very fast transistors. I thought the flat part of the miller region was forced to be the same length as the voltage rise from drain to source?

I suspect I need more gate resistance in any case to lower dv/dt and improve reliability but I am failing to understand why I am seeing the extreme dv/dt I have in the first place. Perhaps someone can set me straight?

[T3sl4co1l]

Heh.  Check the Cgd vs. Vd curve (for either device).  I think you will find your answer...

Or if you look at both signals simultaneously on the scope, you will see Vds rises only a little during the Miller plateau, perhaps in the 5-20V region; then as it passes, the drain voltage accelerates massively.

Curiously, the Cgd drops off precipitously over the same voltage range.  So that's simply it -- almost all the Miller charge is at low voltages.

This helps rather a lot, as it means you don't spend a lot of power taking that time over high voltages instead!

Note that the same occurs as the voltage swings towards the opposite side.  This can be seen here,



A similar circuit, using a pair of 50A 600V IGBTs at 120V or so (it was during a lower voltage test).  Note the slope slows down as it approaches the opposite rail.  This helps to "cushion" the switching transient, as it takes a few nanoseconds longer for the current to transfer from low side to high side.  (Intentionally slowing it, by adding chokes in the source terminals, could have unintended consequences!)

If this is an EMI problem, you might consider dV/dt snubbers.  These can be made low-loss, if ZVS switching can be had, or by using quasi-resonant snubbers.

Tim

[cjk2]

Thanks for the reply.

I gave this some more thought after my first post and came to the conclusion that the turn off is just as important as the turn on of the switch.

Consider this: My half bridges are followed by an inductor and filter cap to form a buck converter. Suppose the low side switch is turned on and current is flowing out of the switching node of the half bridge and through the buck inductor. When the low side switch opens, this current must find an alternative path which is through the body diode of the high side FET. In this process, the switching node swings from 0 to 400V very quickly. In the case of my circuit, the switches open very fast due to the turn off diode I have on the gate resistor.

I suspect I need to remove the diode that is in parallel with the gate resistor to slow turn off to help control the switching speed.

However, in previous testing I found that the diode helped to keep the gate low so the FETs do not turn on due to drain to source dv/dt and cause shoot through. Common source inductance seemed to help with this. I will have to experiment with gate resistance to see if it is safe to remove the turn off diodes.