DDR3 design for a Zynq - strange requirements in the PCB layout guide?

[Korken]

Hi all!

I have started a "small" project revolving around a larger Zynq device, the 7030, and whilst I was selecting which memory to use I had a look in the PCB design guide (UG933) and a few strange things were there that maybe someone here would be able to answer?

1. The routing guidelines forbid T-branch design of DDR3 memories. Does anyone know the reason for this?
My standard approach is to have one memory on top and one on bottom and use T-branch. Very space efficient.
I am aware that fly-by is recommended for DDR3, but the stubs when laying out like this will be extremely short.

2. The length of the traces between the memories in a fly-by design must be exactly 15 mm, why?
I could live with this, but if I have 2 memories next to eachother the length is at its shortest 15.7 mm, so this is concerning.
How have they imagined to route it is what comes to mind.

Any insight is welome!
Thanks!

[DanielS]

My guess would be signal integrity: the IO blocks have been designed to provide some amount of equalization and 15mm fly-by probably puts the IOBs near the middle of their equalization range where they have the best chances of successfully compensating for PCB manufacturing deviations. You can follow the manufacturer's recommendations to have a ~100% chance of achieving a working DRAM layout on the first try or improvise and be on your own.

This is no different than the reference designs for everything else: follow the manufacturer's recommendations to achieve the rated specifications or improvise and find out how far that gets you.

[Alphatronique]

1. The routing guidelines forbid T-branch design of DDR3 memories.

Reflextion 

2. The length of the traces between the memories in a fly-by design must be exactly 15 mm, why?

timing issue

good luck for make a DDR3 bus if you not knot answer on above question ,DDR3 timing was one of the most stiff stuff in PCB  ,need to control impedence ,clock skey ,trace lenght etc etc
so for the long answer ,clock was hight on DDR3 but the raise / falling time was extremely short (< 100ps)  at that speed trace was just like "milimeter radar ' any small discontinutity on impedence
and signal echo back to source , so forgot about put a via on a trace     ,same for trace lenght  have 2mm diference and you got quite good phase lag

but honestly if you never route DDR memory bus  start whit DDR3 was likely result in Failure if you not work whit hi-end PCB package that allow you to simulate it before production 

[c4757p]

but honestly if you never route DDR memory bus  start whit DDR3 was likely result in Failure

My standard approach is

[Korken]

DanielS:
Very true, I will follow the guidelines. I did not know about the equalization though, very interesting.
One day I shall be a rebel and try something different!


Alphatronique:
I know my SI okey at least and I almost always simulate.
Though on the comment on 100ps rise/fall times, the edge is about 15 mm, so stubs that are short compared to that should not be a problem.
But to be sure a proper simulation should be performed to determine the amount of reflection and if it is acceptable.



One final question though, the fly-by length constraint, it is in mm with strict tolerances.
How can this be independent on the dielectric constant of the PCB? As different values will change the electrical delay.
As two worst cases, comparing Er = 3.6 to Er = 4.5 will give about a 10% difference which is outside the 0.1mm tolerance.

[Alphatronique]

Hi

not forgot that you must also consider wire bonding  length  from chip die to pad     (less a problem  now whit flip chip BGA )

so ideally if you not route that kind of stuff every day ,stick to reference design stack-up ,spacing ,material and follow critically all length to sub mm
ideally also try to not use via at all or if use it on all line whit via relatively at same distance from pad and going to same layer ,PCB have 1,6mm thick so it impedence bump and length the traced

if possible try to use DDR1 mutch less issue 

[Alex Eisenhut]

I've done this kind of stuff and I've learned to just copy what already works.

http://www.jedec.org/standards-documents/focus/memory-module-designs-dimms/ddr3/all

[Korken]

Alphatronique:
Indeed, the wire lengths inside the chip must be accounted for, but this is just to export from the Xilinx tools.

On the lengths, this is what bothers me - it does not take the dielectric constant into consideration (yes I have search the entire datasheet).
Length is useless unless you know the dielectric constant for which the length was calculated OR if the length is directly specified in electrical delay.

I will put this question on the Xilinx forum as well, see if I get an answer there.

Alex Eisenhut:
Ah yes, that would be a good reference.
I will see if I can get a confirmation of the distance vs dielectric from one chip to another.

[nctnico]

The 100ps rise/fall translate into 3.5GHz which has a wavelength of 85mm. You could try to simulate what a T-stub does at those frequencies (using Sonnet for example). If it starts to resonate at some frequency things will probrably go wrong.

[Alphatronique]

HI

trace length account on all chip  lay of physic not only apply to FPGA  ,but now it tend to dispersal form datasheet since it use BGA ram chip that less susceptible
that old package ,but fact remain signal must travel this distance to

and yes usually on high end CAD package you not put the length of the trace  ,but the formula  ,then it become bit dynamic ,but on my side still work old way whit external calculator

dielectric consten was for calculate trace spacing / impedence calculation
trace lenght  ,was for timing skew  ,so only need raising/fallinh time speed and material propagation delay  (% of speed of light)
Ex:  when you latch data into bus you what that all signal was set on the ram chip input , may seem strange at first but if bit D3 have 10mm to long ,signal was late versus the other
so it will not latch whit good value     ,

same for clock it ussualy 2 clock  whit 90 phase shift  and it use falling and raising edge so it actually 4 state change per true CLK MHZ  ideally each spaced by 25% of the desired clock
but it one trace was bit longer all quadrature timing become screw 

 __|--|__|--|__|--|__|--|__   <  Clock A = 666mhz
_|--|__|--|__|--|__|--|__    <   Clock B = 666mhz  90 out of phase

combined it  make 1333 whit 50% duty cylcle but as soon A or B move  duty cycle go away really fast ...

so you have 2 chalenge

1-) have really good impedance match every were for avoid signal bonce  and reflection that make ghost signal on he bus

2-) have the right timing  for clock generation  and bit timing   

not forgot that Dram  was dynamic so it refresh in permanence if bus was not perfect it start soon to be error and quickly fail to work  so it have but that work and bus that fail 
and at clock of 1333Mhz  that look instantaneous 

[Korken]

Yeah, you have to be really careful when doing memory layouts!
My motto is usually something like "Simulate twice, design once", to turn an old phrase.

The biggest problem, which also 2D field solvers can't take into account, are stubs.
There are rules of thumb for this, but I usually go here http://www.imx6rex.com and look at Robert's design.
This is also why my questions started to begin with as I usually just copy this design, but he uses T-branch on the clock, but the UG933 forbidds it.
Though, if the stubs are short and balanced the 2 DDR memories  will look like one to the controller.

But I might go away from this and follow Xilinx requirements, even though this is a know working design.
I got answer in the Xilinx forum and the length requirement is 14 mm (sorry wrote 15 mm before).
The controller can write level within a clock cycle or 2, so not 0.1mm.

[sacherjj]

I thought it was design once, simulate once.  Crap.  Design again.  Simulate again.  Crap.  Design again.  Simulate again.  OK, make it and pray.   

[Korken]

Haha, something like that is also included in the process yes.
My problem is that I could not afford the fancy field solvers for entire deisgns, so I have a company I send my finished design to and they look at it and tweaks it if needed.
Though often I just get an "it looks good", but I always do everything in my power to match the requirements.

I just hope that Xilinx will soon give a response on my question regarding having control and address line in T-branch, which is okey from the UG933, but it does not specify the requirements to the clock then.

[AndyC_772]

2. The length of the traces between the memories in a fly-by design must be exactly 15 mm, why?

You sure about this? It's a new one on me.

I can believe that the data bits and strobes must be matched to within 15mm, or perhaps even less than that, but I've not yet come across a device for which the absolute distance is prescribed.

Maybe what they mean is, "we've done a simulation with the spacing at 15mm and it works, so do the same and your board should too"?

FWIW, Freescale has some very good documentation on how to lay out DDR interfaces. The stuff on how to route DDR3 on a QorIQ processor is excellent.

In case anyone's interested, I hear the newest version of Cadence PCB Designer (Standard) is going to have the full-blown SI analysis tool included... quite looking forward to trying it out 

[Korken]

Sorry for my ambiguity, this is for the clock only.
On the Freescale documents, could you provide a link please? Sounds very good to have!

When it comes to the Cadence tools I have never tried them, I was tricked into Altium and now I am stuck.

[AndyC_772]

Go to www.freescale.com and search for AN3940 "Hardware and Layout Design Considerations for DDR3 SDRAM Memory Interfaces - App Note". You'll need to register.

[poorchava]

I thought it was design once, simulate once.  Crap.  Design again.  Simulate again.  Crap.  Design again.  Simulate again.  OK, make it and pray.   

This is pretty much how it looks with custom magnetics. Especially for non-standard applications.

Sent from my HTC One M8s using Tapatalk

[Korken]

Thanks, found the document!