Decapping a MOSFET

[blueskull]

I posted another thread about getting silicon MOSFET dice with no practical solution found yet.
Therefore, I decided to use SiC devices, and I've already designed accordingly.
However, out of curiosity, I just want to see what if I can get dice from packaged devices.

I decapped a Toshiba TK32V60X MOSFET (from its 8mm*8mm DFN package), and the result is here.
During the process, acid etched bonding wire and permeated through bonding pad, leaking into die internally, and created discoloration.
I haven't tested those bare dice yet, but I bet they won't work properly, and even if they work, I won't be comfortable to apply 400V to it.
So the question is, is there a good way of decapping copper wire bonded silicon power devices?





I used 3:1 mixture of 98% H2SO4 and saturated NaNO3. Apparently this stuff is not as good as real HNO3, but buying HNO3 is too expensive, I don't want to spend $50 on its shipping.
I used a 200C hot plate to decap the chip, the chip lies on hot plate, pads side down, marking side up, and I applied acid mixture drop wise and cleaned foaming using the side (not tip) of a pair of tweezers.
It took about 20 minutes to reveal the die, I then cleaned it up a bit using IPA, then desoldered the die from its copper substrate. I did another cleaning and shot the photos.

[Zero999]

Sorry, I can't help.

I do find this interesting. The only question I have is why? Does the package have some undesirable parasitics which mess up the circuit operation or does it to save space?

I've heard about decapping components for educational purposes but never to use.

[tszaboo]

Does the package have some undesirable parasitics which mess up the circuit operation or does it to save space?

To save space. I don't like the 8mm*8mm package while the die is only 4.4mm*5.9mm.

The extra space is there for the very reason you dont like applying 400V to it. 
If you can get away with 250V try DirectFET packages, that is as close as you get to bare dies.

[tszaboo]

And that's where encapsulation comes to rescue.
I'm talking about handling bare dice and wire bonding etc, and I am a PhD in power electronic, specializing in power module packaging.

PhD in my books mean = I have no real experience, but I am close to people who are constantly talking about fairy tales. No offense.

[daqq]

I posted another thread about getting silicon MOSFET dice with no practical solution found yet.

I think Infineon sells bare dice.
http://www.infineon.com/cms/en/product/power/mosfet/power-mosfet-bare-die/channel.html?channel=db3a3043440adf7501440bc6f605009e

A quick google found: http://www.micross.com/fairchild-mosfet-bare-die.aspx

So the question is, is there a good way of decapping copper wire bonded silicon power devices?

Try asking on zeptobars: https://forum.zeptobars.com/viewforum.php?f=4&sid=f96db24ad4ef5f9c4d031509d31b20c5

Not a very popular forum, but they probably look at it occasionally.

[daqq]

The INF bare dice are <=250V devices. I need operating voltage of 400V, so I need 600V or 650V devices.

Oh, OK

Off topic: I'm surprised that contacting the manufacturers directly does not work? I'd assume that they'd be happy to sell you their stuff in whatever form you need.

[tszaboo]

PhD in my books mean = I have no real experience, but I am close to people who are constantly talking about fairy tales. No offense.

I've worked on 650V and 1.2kV power module designs, and I'm working on a 6.5kV module.
Some of my modules have sub nH parasitic inductance and can operate at MHz range, which is extremely rare at 1.2kV voltage level.
I've designed and built 10MHz hard switching GaN VRM, up to 25MHz gate driver and fully optical fiber isolated gate driver for MV switching applications.
I've designed and I'm building a 1MW power converter with our own in-house 6.5kV power module and gate driver module.
I've been a hobbyist of EE and programming since primary school, and the hobbyist excellence gave me qualification to go to a fairly good univ despite I didn't perform well in higher education entrance test.
I received 2 Chinese national undergraduate innovation funding during my undergrad career, and I served as person in charge of our open source community for 2 years.
And I'm now receiving US DoE funding as well as full PhD tuition exemption for developing next generation SiC power modules.

Exactly what I said. SiC and GaN is too expensive, and it will take a decade or two, before they will be economical, and the industry will start using it. Fairy tales. I'm not belittling your achievements. Probably they are very nice, efficient, and elegant. And not economic.
I urge you to get a real job. The enginer's job is to find the best compromise. If you dont have to compromise on price, time, economics, company policy...

[Zero999]

Does the package have some undesirable parasitics which mess up the circuit operation or does it to save space?

To save space. I don't like the 8mm*8mm package while the die is only 4.4mm*5.9mm.

Perhaps a crazy idea but what about machining most of the package away? Of course, you'd then have to figure out a a way to solder to the bond wires.

[james_s]

I don't think you'd ever be able to de-cap a device and end up with a usable die. I certainly would not trust a product that had been built in that way. Surely the savings are not worth the hassle when you can get very small packages already? I suppose you could potentially get dies (dice?) from one of those hybrid packages that is encapsulated in clear goo.

[MagicSmoker]

Yeah, I completely agree with james_s... While it should be trivial to remove the epoxy encapsulation without affecting the die inside, I don't see how you can possibly remove the bond wires from the die metallization as the latter is always the same metal as the (plating, at least) of the former. Not, at least, and still end up with a usable die afterwards.

[ebclr]

Is there any reasonable tool to do wire bonding on chips ?

[rfeecs]

Is there any reasonable tool to do wire bonding on chips ?

What does reasonable mean?  Cheap?  Probably not.
Wire bonder:
http://www.westbond.com/machines_manual_wire_bonders.htm

It is possible to do a thermo-compression bond with just heat and pressure.  That would be the cheapest way to go, but not so easy, especially if the bonding pads are small.

[MagicSmoker]

...I don't see how you can possibly remove the bond wires from the die metallization as the latter is always the same metal as the (plating, at least) of the former. Not, at least, and still end up with a usable die afterwards.

The particular Toshiba MOSFET is an aluminum pad die with copper bonding wire.
Actually I managed to get 2 perfect dice, but only to ruin them in the final cleaning process.
I will see if I have time to decap a new batch, then I will run a probe station test.

Okay, I stand corrected in that there is an exception to the rule that the bond wire and die metallization always use the same metal. That said, how do you remove a copper bond wire from aluminum die metallization without destroying the latter?

[JohnG]

At my old job, I did the opposite, i.e. remove die from package so that I could reuse the package. This was to put SiC MOSFETs in a plastic package for RF power MOSFETs. The work was done by a company called Quik-Pak (www.icproto.com). We would also routinely de-package die in house for examination after stress, so it can be done. I wouldn't trust the die for long-term use, but I understand the need to get bare die. Most companies won't sell modern bare die unless you are buying multiple wafers worth. They don't have a process for it, and they don't see the profit in it.

Exactly what I said. SiC and GaN is too expensive, and it will take a decade or two, before they will be economical, and the industry will start using it. Fairy tales. I'm not belittling your achievements. Probably they are very nice, efficient, and elegant. And not economic.
I urge you to get a real job. The enginer's job is to find the best compromise. If you dont have to compromise on price, time, economics, company policy...

When I started doing electronics, many engineers made exactly the same arguments about power MOSFETs, and how they were unreliable, electrically fragile, unstable in operation, and were not economical compared to power BJTs. Fairy tales, in other words.

They were not incorrect about the problems, but power MOSFETs enabled an order-of-magnitude improvement in power density and loss reduction. The elegance and efficiency ended up resulting in higher profits, and eventually lower cost, once people learned to take advantage of them. Their problems got fixed, and you don't see very many (any?) BJT-based power converters these days. GaN and SiC power semiconductors today are in the same place as MOSFETs were then.