I think some of you might be missing the point of the challenge: you don't get the $1M if you meet the specs, you only win if you are the smallest! Even if meeting the maximum size requirement of 40"sq isn't THAT hard, if someone makes one 39"sq they would win. You need to build it as small as you can and hope nobody builds one any smaller (smaller is baller). I don't want to go into too much details about the challenges associated with this project, where I think you should be looking, as I'm part of a small team of power electronics people taking a serious crack at this (none of us are in it for the money and we're a completely independent team, we are simply driven by building something cool - it's fun).
BTW it is the current requirement that is the 120Hz ripple figure you need to meet. At full power (5A, 400V) you're allowed 1A of ripple with 12V ripple. At lower power say 200W (0.448A, 445.5V) you're allowed 89.7mA ripple but a whopping 13.5V ripple. If you want to use bulk DC capacitance on the bus the worst case scenario is not 100% load, you actually need more DC capacitance to meet the current ripple requirements at lower loads given the 10ohm input impedence.
Some of the topology ideas here are interesting, but that's really only the first step of a long journey. Passives/filter requirements, switching frequency, transistor selection, gate drives, auxillary circuits, cooling, packaging, EMI/EMC, feedback controllers, software... the list goes on. And all the of these factors are related to each other - a huge multivariable problem, how do you optimise it?
It's not called a challenge because it's easy to meet the minimum specifications (I'm not saying it is). It's a challenge because it's hard to build the smallest unit that meets the specs.